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ADE3000 ADE3050 ADE3100 ADE3200 ADE3250 ADE3300
(R)
LCD Display Engines with Integrated DVI, ADC and YUV Ports
The ADE3xxx is a family of highly integrated display engine ICs, enabling the most advanced, flexible, and cost-effective system-on-chip solutions for LCD display applications. The ADE3xxx line-up covers the full range of applications from XGA analog only to dual SXGA Smart Panel designs. All twelve ADE3xxx devices are pin-to-pin compatible and use a common software platform.
Feature Overview
s Programmable Context SensitiveTM Scaling s High-quality up-scaling and down-scaling s Dual Input: DVI / VGA s Integrated 9-bit ADC/PLL s Integrated DVI-Rx s IQSyncTM AutoSetup s Integrated programmable timing controller s Integrated Pattern generator s Perfect PictureTM Technology s sRGB 3D Color Warp s Integrated OSD
s Advanced EMI reduction features s Framelock operation with Safety ModeTM s Serial IC interface s Low power 0.18 m process technology
208-pin PQFP Package
Product Selector
Input Interface Support Product Analog
ADE3000 ADE3000T ADE3000SX ADE3000SXT ADE3050 ADE3050T ADE3050SX ADE3050SXT ADE3100 ADE3200 ADE3250 ADE3300
Output Format Support YUV Resolution
Up to XGA 75Hz Up to XGA 75Hz Up to SXGA 75Hz Up to SXGA 75Hz Up to XGA 75Hz Up to XGA 75Hz Up to SXGA 75Hz Up to SXGA 75Hz Up to XGA 75Hz Up to XGA 75Hz Up to SXGA 75Hz Up to SXGA 75Hz
DVI
TCON
x x x x x x x x x x x x
x x x x
x x x x x x x x x x x x
x x x x x x
October 2003
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ADE3XXX
Third Generation Context SensitiveTM Scaler
q q
Perfect ColorTM Technology
q q
Sharper text with Edge Enhancement RAM based coefficients for unique customization 5:1 upscale and 2:1 downscale Independent X - Y axis zoom and shrink Bob de-interlacing eliminates jaggies and motion artifacts
Programmable 3D color warp Digital brightness, contrast, hue, and saturation gamma controls for all inputs Simple white point control Compatible with sRGB standard True color dithering for 12- and 18-bit panels Temporal and spatial dithering 30-bit programmable gamma table
q q q
q q q q q
Analog RGB input
q q q
140MHz 9-bit ADC Ultra low jitter digital linelock PLL Composite Sync and Sync on Green support
OSD Engine
q q q
256 RAM based 12x18 characters 1 and 4-bit per pixel color characters Bordering, shadowing, transparency, fade-in, and fade-out Supports font rotation Up to 4 sub windows 32 entry TrueColor LUT
Secure DVITM Receiver
q q q q
Single Link DVI receiver Input Pixel Rate from 25 to140 MHz Low power mode with activity detection Compatibility with all DVI compliant transmitters
q q q
Programmable Timing Controller (TCON)
q
Digital TV Video Input
q q
VESA VIP 1.1, 2.0 and CCIR656 compliant 25 to 75 MHz input clock
q q q
Highly-programmable support for XGA, TTL and RSDS SmartPanels Dual function TTL and RSDS outputs Advanced flicker detection and reduction 12 programmable timing signals for row/ column control Wide range of drivers & TCON compatibility Simulation tools for easy programming Supports complex polarity generation for IPS panels
IQsyncTM AutoSetup
q
AutoSetup configures phase, clock, level, and position Supports continuous calibration for reduced user intervention Detects activity on all inputs and selects the active source Compatible with all standard VESA and GTF modes
q
q q q
q
q
Advanced EMI Reduction Features
q
Perfect PictureTM Technology
q q q
Flexible data inversion / transition minimization, single, dual, and separate Per pin delay, 0 to 6ns in 0.4ns increments Adaptive Slew Rate control outputs Supports 18/24/36/48-bit RSDS outputs Differential clock Spread spectrum -programmable digital FM modulation of the output clock with no external components
Video & Picture highlight zoning Supports up to 7 different windows Independent window controls for contrast brightness, sharpness, and color
q q q q q
Output Format
q q q
Supports resolutions up to SXGA @ 75Hz Supports 6 or 8-bit Panels Support double or single pixel wide formats
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ADE3XXX
Table of Contents
Chapter 1
1.1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Pin Description .................................................................................................................... 6
Chapter 2
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12
ADE3XXX Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Global Control Block .......................................................................................................... 13 FM Frequency Synthesizer ................................................................................................ 17 ADC Block .......................................................................................................................... 18 Line Lock PLL Block ........................................................................................................... 19 Digital Video Input (DVI) ..................................................................................................... 22 HDCP Block ....................................................................................................................... 27 YUV Block .......................................................................................................................... 29 Sync Retiming Block .......................................................................................................... 30 Sync Measurement Block .................................................................................................. 32 Sync Mux Block .................................................................................................................. 40 Data Mux Block .................................................................................................................. 42 Data Measurement Block ................................................................................................... 42
2.12.1 2.12.2 2.12.3 2.12.4 2.12.5 2.12.6 2.12.7 Edge Intensity ....................................................................................................................................43 Pixel Sum ...........................................................................................................................................43 Min / Max ...........................................................................................................................................43 PCD ...................................................................................................................................................43 H Position Min / Max ..........................................................................................................................43 V Position Min / Max ..........................................................................................................................44 DE Size ..............................................................................................................................................44
2.13 2.14 2.15
Programmable Nonlinearity Block ...................................................................................... 48 Scaler Block ....................................................................................................................... 49 Output Sequencer Block .................................................................................................... 52
Frame Synchronization .......................................................................................................................................52 Timing Unit ..........................................................................................................................................................52 Signal Generation ...............................................................................................................................................52
2.16 2.17
Timing Controller (TCON) Block ........................................................................................ 55 Pattern Generator Block ..................................................................................................... 60
Screen Split ........................................................................................................................................................60 Pattern Engine ....................................................................................................................................................61 Borders ...............................................................................................................................................................61
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ADE3XXX
2.18 SRGB Block ........................................................................................................................64
2.18.1 2.18.2 Parametric Gamma Correction and Digital Contrast/Brightness Control .......................................... 64 Color Space Warp ............................................................................................................................. 64
2.19 2.20 2.21 2.22 2.23 2.24 2.25 2.26
OSD Block ..........................................................................................................................66 Flicker Block .......................................................................................................................72 Gamma Block .....................................................................................................................74 APC Block ..........................................................................................................................74 Output Mux Block ...............................................................................................................75 Pulse Width Modulation (PWM) Block ................................................................................77 DFT Block ...........................................................................................................................79 IC RAM Addresses ...........................................................................................................80
Chapter 3
3.1 3.2 3.3 3.4 3.5
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Absolute Maximum Ratings ................................................................................................82 Power Consumption Matrices .............................................................................................82 Nominal Operating Conditions ............................................................................................83 Preliminary Thermal Data ...................................................................................................84 Preliminary DC Specifications ............................................................................................84
3.5.1 3.5.2 3.5.3 3.5.4 LVTTL 5 Volt Tolerant Inputs With Hysteresis ................................................................................... 84 LVTTL 5 Volt Tolerant Inputs ............................................................................................................. 84 LVTTL 5 Volt Tolerant I/O With Hysteresis ........................................................................................ 84 LVTTL Outputs .................................................................................................................................. 84
3.6
Preliminary AC Specifications ...........................................................................................85
Chapter 4 Chapter 5
Package Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
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ADE3XXX
1
General Description
Figure 1: ADE3XXX Block Diagram
YUV Port
DMEAS
Color Management OSD
Gamma LUT
SMEAS DVI Port SCLK F. Synth DATA CTRL LLKPLL INCLK SCLK P. Gen FM F. Synth
DOTCLK
The ADE3XXX family of devices is capable of implementing all of the advanced features of today's LCD monitor products. For maximum flexibility, an external microcontroller (MCU) is used for controlling the ADE3XXX and other monitor functions. The ADE3XXX architecture unburdens the MCU from all data-intensive pixel manipulations, providing an optimal blend of feature and code customization without incurring the cost of a 16-bit processor or memory. The key interactions between the monitor MCU and the ADE3XXX can be broken down into the features shown in the table below.
Table 1: ADE3xxx Features (Sheet 1 of 2) Feature Description of ADE3XXX Operation Blocks Used
GLBL SMEAS DVI LLK ADC YUV OSD SCALER GAMMA SRGB OUTSEQ TCON APC OMUX
Pages
13 32 22 19 18 29 66 49 74 64 52 55 74 75 32
Power Up / Initialize When power is first applied, the ADE3XXX is asynchronously reset from a pin. The MCU typically programs the ADE3XXX with a number of default values and sets up the ADE3XXX to identify activity on any of the input pins. All preconfigured values and RAMs, such as DVI settings, line-lock PLL settings, video input modes (YUV), OSD characters, LCD timing values (output sequencer), scale kernels, gamma curves, sRGB color warp, APC dithering, output pin configuration (OMUX), etc. can be preloaded into the ADE3XXX. The typical end state is that the ADE3XXX is initialized into a low power mode, ready to turn active once the power button is pressed.
Activity Detect
When the monitor has been powered on, the inputs can be monitored for active SMEAS video sources. Based on the activity monitors, the MCU chooses an input or power down state.
Output Format
Analog Port
Scaler with Vertical Keystone
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Pin Description
Table 1: ADE3xxx Features (Sheet 2 of 2) Feature
Sync / Timing Measurement Mode Set
ADE3XXX
Description of ADE3XXX Operation
Blocks Used
Pages
32
Once an input source is selected, all available information on frequencies and SMEAS line/pixel counts is measured for the selected source and made available to the MCU. Once the MCU has determined the matching video mode or calculated a video GLBL mode using a GTF algorithm, the datapath is programmed to drive the flat panel. LLK Clock frequencies for the internal memory and datapath are also set at this time. SRT DMUX SMUX SCALER PNL When the MCU calls for an autotune, the MCU sets up an iterative loop to search for the best phase, gain, offset, etc. At each step of the loop, the MCU kicks off a test in which the ADE3XXX which performs extensive statistical analysis of the incoming data stream. The results of the analysis are made available to the MCU which is responsible for the optimization algorithm. DMEAS LLK ADC SMUX SRT
13 19 30 42 40 49 48 47 19 18 40 30 64 64 74 64 60 72 55 27
Autotune
Digital Contrast / Brightness
In response to user OSD control, the MCU can program single 8b registers that SRGB set brightness and contrast for each color channel independently. SRGB GAMMA SRGB
White Point Control In response to user OSD control, the MCU can program three 8b registers that set the white point for the output. Gamma Adjustment SRGB Control Pattern Generation Flicker Reduction The MCU can program the gamma RAMs to implement 10b accurate color transformations. The SRGB block allows simple, intuitive color control with just a few registers.
For production testing, the ADE3XXX can be programmed by the MCU to output PGEN a wide set of test patterns. For smart panel applications, the MCU can set up the flicker detection block to report any correlation with the polarity inversion signal. The MCU can then change the polarity inversion to a non-correlating pattern to eliminate flicker. FLICKER TCON
HDCP
The ADE3XXX contains the BlockCipher and Decryption functions - interactions HDCP over DDC are managed by the MCU for maximum flexibility. The MCU models the slow (frame rate, e.g. 60 Hz) authentication handshaking and state machine whereas the ADE3XXX handles the fast (line rate, e.g. 50 kHz) decryption state machine. The ADE3XXX provides two PWM outputs for direct control of the power components in a typical backlight. The MCU sets up the registers and enables the function. PWM
Backlight Control
77
Low Power State
To enter a low power state, the MCU can gate of most of the clocks and put the GLBL analog blocks into a low power standby state. The DVI block will still report activity in standby, allowing "wake on connection" operation.
13
1.1
Pin Description
Table 2: Pin Description (Sheet 1 of 7) Pin #
1 2 3 4 5 YUV6 YUV5 YUV4 YUV3 YUV2
Name
Type
Input Input Input Input Input
Description
TV Video Input Port: Data 6 TV Video Input Port: Data 5 TV Video Input Port: Data 4 TV Video Input Port: Data 3 TV Video Input Port: Data 2
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ADE3XXX
Table 2: Pin Description (Sheet 2 of 7) Pin #
6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 YUV1 YUV0 YUVCLK DVDD18 DGND DVDD18 DGND AGND AVDD18 AVDD33 RX2M RX2P AGND AVDD33 RX1M RX1P AVDD33 RX0M RX0P AVDD33 AGND RXCP RXCM AVDD33 REXT AVDD33 AVDD33 AGND AGND AGND RBIAS AGND AVDD18 AGND AVDD33 AGND AVDD18 AGND AVDD18
Pin Description
Name
Type
Input Input Input Power Power Power Power Power Power Power Input Input Power Power Input Input Power Input Input Power Power Input Input Power Passive Power Power Power Power Power Passive Power Power Power Power Power Power Power Power
Description
TV Video Input Port: Data 1 TV Video Input Port: Data 0 TV Video Input Port: Clock Digital 1.8V VDD Digital Ground Digital 1.8V VDD Digital Ground Analog Ground Analog 1.8V VDD Analog 3.3V VDD DVI Receiver Channel 2 MINUS input (RED) DVI Receiver Channel 2 PLUS input (RED) Analog Ground Analog 3.3V VDD DVI Receiver Channel 1 MINUS input (GREEN) DVI Receiver Channel 1 PLUS input (GREEN) Analog 3.3V VDD DVI Receiver Channel 0 MINUS input (BLUE) DVI Receiver Channel 0 PLUS input (BLUE) Analog 3.3V VDD Analog Ground DVI Receiver Clock Channel PLUS input DVI Receiver Clock Channel MINUS input Analog 3.3V VDD 1% 475 Ohm resistor to Analog 3.3V VDD Analog 3.3V VDD Analog 3.3V VDD Analog Ground Analog Ground Analog Ground 1% 2.0 kOhm resistor to Analog Ground Analog Ground Analog 1.8V VDD Analog Ground Analog 3.3V VDD Analog Ground Analog 1.8V VDD Analog Ground Analog 1.8V VDD
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Pin Description
Table 2: Pin Description (Sheet 3 of 7) Pin #
45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 AGND AVDD18 XGND XTAL_IN XTAL_OUT XVDD18 LVDD18 LGND CSYNC VSYNC HSYNC AGND AGND AVDD33 AVDD33 AGND AVDD18 AGND REFB REFMB REFPB AGND AGND INB AVDD33 AVDD33 REFCB AGND AVDD18 AVDD18 REFG REFMG REFPG AGND AGND ING AVDD33 AVDD33 REFCG
ADE3XXX
Name
Type
Power Power Power Input Output Power Power Power Input Input Input Power Power Power Power Power Power Power Passive Passive Passive Power Power Input Power Power Passive Power Power Power Passive Passive Passive Power Power Input Power Power Passive Analog Ground Analog 1.8V VDD Crystal Oscillator Ground Crystal Oscillator Input Crystal Oscillator Output
Description
Crystal Oscillator 1.8V VDD Line Lock PLL 1.8V VDD Line Lock PLL Ground Composite Sync Input - for Sync On Green Vertical Sync Input Horizontal (or Composite) Sync Input Analog Ground Analog Ground Analog 3.3V VDD Analog 3.3V VDD Analog Ground Analog 1.8V VDD Analog Ground 1% 15.0 kOhm resistor to Analog Ground Connect to Analog Ground 470nF capacitor to Analog Ground Analog Ground Analog Ground Analog Video Port: Blue Channel input Analog 3.3V VDD Analog 3.3V VDD 100nF capacitor to Analog Ground Analog Ground Analog 1.8V VDD Analog 1.8V VDD 1% 15.0 kOhm resistor to Analog Ground Connect to Analog Ground 470nF capacitor to Analog Ground Analog Ground Analog Ground Analog Video Port: Green Channel input Analog 3.3V VDD Analog 3.3V VDD 100nF capacitor to Analog Ground
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ADE3XXX
Table 2: Pin Description (Sheet 4 of 7) Pin #
84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 AGND AVDD18 AVDD18 REFR REFMR REFPR AGND AGND INR AVDD33 AVDD33 REFCR AGND AVDD18 AVDD18 TST_SCAN DGND DVDD33 OBA7 OBA6 OBA5 DGND OBA4 OBA3 OBA2 OBA1 OBA0 DVDD33 DGND OGA7 OGA6 OGA5 OGA4 OGA3 OGA2 OGA1 OGA0 DVDD18 DGND
Pin Description
Name
Type
Power Power Power Passive Passive Passive Power Power Input Power Power Passive Power Power Power Input Power Power Output Output Output Power Output Output Output Output Output Power Power Output Output Output Output Output Output Output Output Power Power Analog Ground Analog 1.8V VDD Analog 1.8V VDD
Description
1% 15.0 kOhm resistor to Analog Ground Connect to Analog Ground 470nF capacitor to Analog Ground Analog Ground Analog Ground Analog Video Port: Red Channel input Analog 3.3V VDD Analog 3.3V VDD 100nF capacitor to Analog Ground Analog Ground Analog 1.8V VDD Analog 1.8V VDD Connect to Digital Ground Digital Ground Digital 3.3V VDD Output Port A: Blue Data 7 Output Port A: Blue Data 6 Output Port A: Blue Data 5 Digital Ground Output Port A: Blue Data 4 Output Port A: Blue Data 3 Output Port A: Blue Data 2 Output Port A: Blue Data 1 Output Port A: Blue Data 0 Digital 3.3V VDD Digital Ground Output Port A: Green Data 7 Output Port A: Green Data 6 Output Port A: Green Data 5 Output Port A: Green Data 4 Output Port A: Green Data 3 Output Port A: Green Data 2 Output Port A: Green Data 1 Output Port A: Green Data 0 Digital 1.8V VDD Digital Ground
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Pin Description
Table 2: Pin Description (Sheet 5 of 7) Pin #
123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 DVDD18 DGND DVDD33 ORA7 ORA6 ORA5 ORA4 ORA3 ORA2 ORA1 ORA0 DVDD33 DGND ODE OHS OCLK OVS DVDD18 DGND DVDD18 DGND OBB7 OBB6 OBB5 OBB4 DVDD33 DGND OBB3 OBB2 OBB1 OBB0 OGB7 OGB6 OGB5 OGB4 DVDD33 DGND OGB3 OGB2
ADE3XXX
Name
Type
Power Power Power Output Output Output Output Output Output Output Output Power Power Output Output Output Output Power Power Power Power Output Output Output Output Power Power Output Output Output Output Output Output Output Output Power Power Output Output Digital 1.8V VDD Digital Ground Digital 3.3V VDD
Description
Output Port A: Red Data 7 Output Port A: Red Data 6 Output Port A: Red Data 5 Output Port A: Red Data 4 Output Port A: Red Data 3 Output Port A: Red Data 2 Output Port A: Red Data 1 Output Port A: Red Data 0 Digital 3.3V VDD Digital Ground Output Data Enable Output Horizontal Sync Output Clock Output Vertical Sync Digital 1.8V VDD Digital Ground Digital 1.8V VDD Digital Ground Output Port B: Blue Data 7 Output Port B: Blue Data 6 Output Port B: Blue Data 5 Output Port B: Blue Data 4 Digital 3.3V VDD Digital Ground Output Port B: Blue Data 3 Output Port B: Blue Data 2 Output Port B: Blue Data 1 Output Port B: Blue Data 0 Output Port B: Green Data 7 Output Port B: Green Data 6 Output Port B: Green Data 5 Output Port B: Green Data 4 Digital 3.3V VDD Digital Ground Output Port B: Green Data 3 Output Port B: Green Data 2
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ADE3XXX
Table 2: Pin Description (Sheet 6 of 7) Pin #
162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 OGB1 OGB0 DVDD18 DGND DVDD18 DGND ORB7 ORB6 ORB5 ORB4 DVDD33 DGND ORB3 ORB2 ORB1 ORB0 DVDD18 DGND DVDD18 DGND CLKOUT CLKIN TCON_IN DVDD33 DGND TCON7 TCON6 TCON5 TCON4 DVDD18 DGND DVDD18 DGND TCON3 TCON2 TCON1 TCON0 DVDD18 DGND
Pin Description
Name
Type
Output Output Power Power Power Power Output Output Output Output Power Power Output Output Output Output Power Power Power Power Output Input Input Power Power Input/Output Input/Output Input/Output Input/Output Power Power Power Power Input/Output Input/Output Input/Output Input/Output Power Power
Description
Output Port B: Green Data 1 Output Port B: Green Data 0 Digital 1.8V VDD Digital Ground Digital 1.8V VDD Digital Ground Output Port B: Red Data 7 Output Port B: Red Data 6 Output Port B: Red Data 5 Output Port B: Red Data 4 Digital 3.3V VDD Digital Ground Output Port B: Red Data 3 Output Port B: Red Data 2 Output Port B: Red Data 1 Output Port B: Red Data 0 Digital 1.8V VDD Digital Ground Digital 1.8V VDD Digital Ground Not to be connected - Reserved To be connected to Digital Ground - Reserved TCON input Digital 3.3V VDD Digital Ground TCON Output 7/YUV Input 15 TCON Output 6/YUV Input 14 TCON Output 5/YUV Input 13 TCON Output 4/YUV Input 12 Digital 1.8V VDD Digital Ground Digital 1.8V VDD Digital Ground TCON Output 3/YUV Input 11 TCON Output 2/YUV Input 10 TCON Output 1/YUV Input 9 TCON Output 0/YUV Input 8 Digital 1.8V VDD Digital Ground
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Pin Description
Table 2: Pin Description (Sheet 7 of 7) Pin #
201 202 203 204 205 206 DVDD18 DGND SCL SDA XCLK XCLK_EN
ADE3XXX
Name
Type
Power Power Input Digital 1.8V VDD Digital Ground I2C Clock
Description
Open Drain I/O I2C Data Output Input Crystal Clock Buffered Output Crystal Clock Output Enable 0: XCLK output disabled 1: XCLK output active
207 208
RESETN YUV7
Input Input
Reset input (Active Low) TV Video Input Port: Data 7
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ADE3XXX
Global Control Block
2
2.1
ADE3XXX Functional Description
Global Control Block
The global control block is responsible for:
q q q q q
Selecting Clock Sources Power Control IC Control SCLK Frequency Synthesizer Control Block-by-Block Synchronous Reset Generation
The global control block runs on the XCLK clock domain which is required to be active for programming. The clock domains of all other blocks are set in the Global Control Block. For IC access, the requested block must be driven with a valid clock above 10 MHz. Clock domains are shown in Figure 2.
Figure 2: Clock Domains
Microcontroller
SCL, SDA
I2C Global
PWM
Sync Measure Sync Re-Time
ADE3XXX
Flicker Detect
XCLK domain
YUV Video
YUV, YUVCLK
YUV to RGB
data SMUX
DVI Link
RX0-2, RXC
Pattern Gen.
DVI Rx (Analog) DVI Decoder HDCP
sync
ORA, OGA, OBA
Gamma
sRGB
OSD
Scaler
APC
PNL
sync
data
Output Mux
ORB, OGB, OBB
OCLK
PC Analog
INR, G, B V,H,CSYNC
ADC (Analog) ADC Digital I/F
data
DMUX
Data Measure
Output Sequencer SCLK Freq.Synth. TCON
ODE, OHS, OVS
TCON
Line Lock PLL
INCLK domain
SCLK domain
DOTCLK domain
FM Freq. Synth.
To program the SCLK frequency synthesizer to a desired frequency (fout, in MHz), the following equations apply:
Table 3: SCLK Frequency Ranges Frequency Range
fOUT < 8 x fXCLK AND fOUT 4 x fXCLK fOUT < 4 x fXCLK AND fOUT 2 x fXCLK fOUT < 2 x fXCLK AND fOUT fXCLK
SDIV
0 1 2
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Global Control Block
Table 3: SCLK Frequency Ranges (Continued) Frequency Range
fOUT < fXCLK AND fOUT fXCLK /2 fOUT < fXCLK/2 AND fOUT fXCLK /4 fOUT < fXCLK/4 AND fOUT fXCLK /8 fOUT < fXCLK/8 AND fOUT fXCLK /16 fOUT < fXCLK/16 AND fOUT fXCLK /32
ADE3XXX
SDIV
3 4 5 6 7
MD = INT(fXCLK x (2(6 + NDIV - SDIV)) / fOUT) PE = INT((215) x (MD + 1 - fXCLK x (2(6 + NDIV - SDIV)) / fOUT)) where fXCLK is the external crystal frequency in MHz (typically 27). The maximum SCLK frequency generated by this block is fXTAL x 2(2+NDIV). For lower power operation, set all clock sources to the "zero" setting and also set the analog power disables. In this condition, only the crystal clock domain (XCLK) runs and blocks in INCLK or DOTCLK domains are not accessible by I2C. To detect a DVI plug event and wake from a low power state, program the DVI detection clock source select to the DVI detect clock and enable the analog power control for the DVI detect clock. All other clock sources are set to zero.
Table 4: Global Registers (Sheet 1 of 4) Register Name
GLBL_NULL_ADDR GLBL_CLK_SRC_SEL_0
Addr.
0x0000 0x0001
Mode
R/W
Bits
[7:0] [7]
Default
0x0 0x0 0x5
Description
Chip Revision ID Reserved DOTCLK source 0x0: YUVCLK pin 0x1: SCLK freq synth 0x2: FM freq synth (normal) 0x3: INCLK 0x4: CLKIN pin 0x5: crystal clock 0x6: 0 0x7: Reserved
R/W
[6:4]
R/W
[3:0]
0xA
INCLK source 0x0: YUVCLK pin (YUV Input) 0x1: DVI_PLLCLK (DVI Input) 0x2: ADCclock red 0x3: ADCclock green 0x4: ADC clock blue 0x5: SCLK freq synth 0x6: DVI detect clock 0x7: LLK PLL (ADC Input) 0x8: CLKIN pin 0x9: FM freq synth 0xA: crystal clock 0xB: 0 0xC - 0xF: Reserved
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ADE3XXX
Table 4: Global Registers (Sheet 2 of 4) Register Name
GLBL_CLK_SRC_SEL_2
Global Control Block
Addr.
0x0002
Mode
Bits
[7]
Default
0x0 0x4 Reserved
Description
R/W
[6:4]
LLK CTRL CLK source 0x0: YUVCLK pin 0x1: SCLK freq synth 0x2: LLKPLL control clock (normal) 0x3: CLKIN pin 0x4: crystal clock 0x5: 0 0x6 - 0x7: Reserved
[3] R/W [2:0] 0x4
Reserved LLK ZERO CLK source 0x0: YUVCLK pin 0x1: SCLK freq synth 0x2: LLKPLL zero clock (normal) 0x3: CLKIN pin 0x4: crystal clock 0x5: 0 0x6 - 0x7: Reserved
GLBL_CLK_INV
0x0003 R/W R/W R/W R/W R/W R/W R/W
[7] [6] [5] [4] [3] [2] [1] [0] [7:5] R/W R/W R/W R/W R/W [4] [3] [2] [1] [0] [7:3] R/W R/W R/W [2] [1] [0] [7:3] R/W R/W R/W [2] [1] [0] [7:1] R/W [0]
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x1 0x1 0x1 0x1 0x1 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x1
Reserved Invert YUV clock Invert DVI detect clock Invert ADC clock Invert LLPLL zero clock Invert LLPLL ctrl clock Invert DOT clock Invert input clock Reserved Blue ADC power down Green ADC power down Red ADC power down DVI detect clock power down DVI PLL power down Reserved SMEAS block reset, synchronous to XCLK SRT block reset, synchronous to XCLK Frame sync block reset, synchronous to XCLK Reserved Disable I2C auto increment SDA PMOS enable Bypass I2C filter Reserved Crystal Oscillator Enable
GLBL_ANA_PWR
0x0005
GLBL_XK_SRST
0x0006
GLBL_I2C_CTRL
0x0007
GLBL_XTAL_CTRL
0x0008
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Global Control Block
Table 4: Global Registers (Sheet 3 of 4) Register Name
GLBL_SCLK_SYNTH_CTRL
ADE3XXX
Addr.
0x0009
Mode
Bits
[7:5]
Default
0x0 0x0 Reserved
Description
R/W
[4:3]
XTAL frequency multiplier NDIV 0x0: fXCLK = 54MHz 0x1: fXCLK = 27MHz (normal) 0x2: fXCLK = 13.5MHz 0x3: Reserved
R/W R/W R/W GLBL_SCLK_MD_SD 0x000A R/W R/W GLBL_SCLK_PE_L GLBL_SCLK_PE_H GLBL_TST_CTRL 0x000B 0x000C 0x000D R/W GLBL_ADC_CLK_SRC_SEL R/W R/W R/W
[2] [1] [0] [7:3] [2:0] [7:0] [7:0] [7:1] [0] [7:3] [2:0]
0x0 0x0 0x1 0x0 0x0 0x0
SCLK frequency synthesizer EXT_PLL (normal operation = 0) SCLK frequency synthesizer PLL_SEL (normal operation = 1) SCLK freq synth control disable (normal operation = 0) SCLK frequency synthesizer MD, range is [16,31] SCLK frequency synthesizer SDIV, range is [0,7] SCLK frequency synthesizer PE, range is [0, 32767]
0x0 0x0
Reserved Functional Test Mode Enable Reserved
0x5
ADC Sample Clock Source 0x0: YUVCLK pin 0x1: LLK_PLL (normal) 0x2: SCLK freq synth 0x3: CLKIN pin 0x4: FM freq synth 0x5: Crystal Clock 0x6: 0 0x7: Reserved
GLBL_SCLK_CTRL
0x0010 R/W
[7:5] [4] [3] R/W [2:0]
0x0 0x0
Reserved Invert SCLK Reserved
0x0
SCLK source select 0x0: YUVCLK pin 0x1: SCLK freq synth 0x2: FM freq synth (normal) 0x3: inclk source 0x4: CLKIN pin 0x5: crystal clock 0x6: 0 0x7: Reserved
GLBL_TCON_BPAD_EN
0x0011
R/W
[7:0]
0x0
For each bit n (0 to 7), 0: TCON[n] pin is TCON output 1: TCON[n] pin is input into TVI block
16/88
ADE3XXX
Table 4: Global Registers (Sheet 4 of 4) Register Name
GLBL_CLK_SRC_SEL_3
FM Frequency Synthesizer
Addr.
0x0012
Mode
Bits
[7]
Default
Reserved 0x4
Description
R/W
[6:4]
YUV clock source 0x0: YUVCLK pin 0x1: SCLK freq synth 0x2: YUVCLK pin (normal) 0x3: CLKIN pin 0x4: crystal clock 0x5: 0 0x6 - 0x7: Reserved
[3] R/W [2:0] 0x4
Reserved DVI detection clock source 0x0: YUVCLK pin 0x1: SCLK freq synth 0x2: DVI detect clock (normal) 0x3: CLKIN pin 0x4: crystal clock 0x5: 0 0x6 - 0x7: Reserved
GLBL_IK_SRST
0x0020
R/W R/W R/W R/W R/W R/W R/W R/W
[7] [6] [5] [4] [3] [2] [1] [0] [7]
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
HDCP block reset synchronous to INCLK DFT block reset synchronous to INCLK ADC block reset synchronous to INCLK SCALER block reset synchronous to INCLK YUV block reset synchronous to INCLK DVI block reset synchronous to INCLK DMEAS block reset synchronous to INCLK SMUX block reset synchronous to INCLK Reserved PGEN block reset synchronous to DOTCLK OMUX block reset synchronous to DOTCLK APC block reset synchronous to DOTCLK OSD block reset synchronous to DOTCLK GAMMA block reset synchronous to DOTCLK OSQ block reset synchronous to DOTCLK SCALE block reset synchronous to DOTCLK
GLBL_DK_SRST
0x0040 R/W R/W R/W R/W R/W R/W R/W
[6] [5] [4] [3] [2] [1] [0]
2.2
FM Frequency Synthesizer
The FM frequency synthesizer creates a clock equivalent to up to eight times the crystal input clock, using a digital frequency synthesizer. The modulation period and amplitude are directly controlled by I2C registers. The I2C interface runs in the LLK_CTRL clock domain, which must be active for access. The output frequency (fOUT) is related to the 32-bit PHASE_RATE and crystal frequency (fXCLK) as follows: fOUT = fXCLK x 227+NDIV / PHASE_RATE
17/88
ADC Block
where fOUT and fXCLK are in MHz. The maximum output frequency of the fm frequency synthesizer is fXTAL x 2(2+NDIV).
ADE3XXX
Note that native duty cycle of the fm frequency synthesizer is not 50/50. We recommend to either enable the divide-by-two in the fm synthesizer block for frequencies up to fXCLK x 2(1+NDIV) (typically 108 MHz) or set the output mux to a double wide output mode for pixel clocks above fXCLK x 2(1+NDIV). This will ensure a 50% duty clock on the output.
Table 5: FM Frequency Synthesizer Registers Register Name
FM_FS_CTRL
Addr
0x0830
Mode
Bits
[7:4]
Default
Reserved 0x0 0x0 0x0 0x0
Description
R/W R/W R/W R/W FM_FS_PR_0 FM_FS_PR_1 FM_FS_PR_2 FM_FS_PR_3 FM_FS_AMPLITUDE FM_FS_PERIODX64 0x0831 0x0832 0x0833 0x0834 0x0835 0x0836 R/W R/W R/W R/W R/W R/W
[3] [2] [1] [0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0]
Clear the FM synthesizer Clear the FS accumulator Activate the frequency modulation Divide the output by 2
0x8000000 Phase Rate
0x0 0x80
LSB = 72 ps LSB = 1.185 s
2.3
ADC Block
The analog port consists of three 9-bit RGB ADCs with preamp, gain/offset adjustment and digital filtering. The I2C interface for the ADC block is in the INCLK clock domain which must be active for programming. Input voltage, gain and offset register settings are approximately related to the output code. In this equation, the output code (OUTPUT_CODE_8B) is equal to: 457 x offset / 28 + 181 x gain x input_mV / 216 - 125 x gain x offset / 216 - 219
Table 6: ADC Registers Register Addr.
0x0324 R/W R/W R/W R/W R/W
Mode
Bits
[7] [6] [5] [4] [3] [2] [1:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0]
Default
Reserved 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
Description
Dither Horizontally Dither Vertically Dither Temporally Force Dither High Enable Dither Reserved Offset Control, Red Channel Offset Control, Green Channel Offset Control, Blue Channel Gain Control, Red Channel Gain Control, Green Channel Gain Control, Blue Channel
ADC_DITHER
ADC_OFFSET_R ADC_OFFSET_G ADC_OFFSET_B ADC_GAIN_R ADC_GAIN_G ADC_GAIN_B
0x0326 0x0328 0x0329 0x032A 0x032B 0x032C
R/W R/W R/W R/W R/W R/W
18/88
ADE3XXX
Line Lock PLL Block
2.4
Line Lock PLL Block
The line lock PLL recovers a sample clock from an incoming hsync source. The response characteristics of the line lock PLL are adjustable for optimimum response time and jitter filtering. The phase of the sample clock is digitally adjustable by steps of 289 ps (with a 27-MHz crystal). The I2C interface of the line lock PLL is in the LLK_CTRL clock domain which must be active for programming. The PLL loop filter has three ranges with independent filter parameters. When the phase detector error remains below a programmable threshold for a programmable number of input lines, the loop filter coefficients change. Any phase detector error above the programmed threshold reverts the filter to the appropriate level in one line. The operation is represented in Figure 3.
Figure 3: Line Lock PLL State Diagram
error <= SLOW_TOL for more than SLOW_LINE_NB of lines error <= LOCK_TOL for more than LOCK_LINE_NB of lines
fast
slow
lock
error > SLOW_TOL
error > LOCK_TOL
The digital loop filter is controlled by three parameters: MFACTOR, A and B. M_FACTOR is the desired number of clocks per input line. The A and B parameters control the response of the 2nd order digital filter. A and B are composed of a linear and exponential component designated by the L and E suffix, respectively. These numbers are related to the classic 2nd order damping and natural frequency as follows: Damping = AL x 2(AE-12) x SQRT(5 x M_FACTOR / (BL x 2BE)) Natural Frequency = SQRT(M_FACTOR x 5 x BL x 2(BE-34))
Table 7: Line Lock PLL Registers (Sheet 1 of 4) Register Name
LLK_PLL_CLEAR
Addr
0x0800
Mode
Bits
[7:6]
Default
Reserved 0x0 0x0 0x0 0x0 0x0 0x0 Master Reset
Description
R/W R/W R/W R/W R/W R/W
[5] [4] [3] [2] [1] [0]
Reset the PLL synthetic sync Reset PLL offset Reset PLL accumulator Reset the low pass filter Reset the PLL phase error
19/88
Line Lock PLL Block
Table 7: Line Lock PLL Registers (Sheet 2 of 4) Register Name
LLK_PLL_CTRL
ADE3XXX
Addr
0x0801
Mode
R/W R/W
Bits
[7:6] [5]
Default
Reserved 0x0
Description
0: normal 1: diagnostic mode -- PLL uses only fine error 0: normal 1: diagnostic -- coarse error is multiplied by 2 input hsync edge selection 0: rising edge 1: falling edge
R/W
[4]
0x0
R/W
[3]
0x0
R/W
[2]
0x0
sync on green input selection 0: composite sync (HSYNC pin) 1: sync on green (CSYNC pin)
R/W R/W LLK_PLL_MFACTOR_L LLK_PLL_MFACTOR_H LLK_PLL_HPERIOD_L LLK_PLL_HPERIOD_H LLK_PLL_PHASE_RATE_INIT_0 LLK_PLL_PHASE_RATE_INIT_1 LLK_PLL_PHASE_RATE_INIT_2 LLK_PLL_PHASE_RATE_INIT_3 LLK_PLL_PHASE_RATE_INIT_WR 0x0802 0x0803 0x0804 0x0805 0x0806 0x0807 0x0808 0x0809 0x080A R/W R/W R/W R/W R/W R/W R/W R/W R/W
[1] [0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:1] [0]
0x0 0x0 0x0280
0: normal 1: divide PLL clock by 2 0: normal 1: Free-running mode number of clocks in a line
0x0040
pulse width of synthetic hsync
0x0
Initial Phase Rate fOUT = fXTAL x 227+NDIV / PHASE_RATE
Reserved When written to 1, the PLL phase rate is initialized with the initial phase rate register. Self clearing. Reserved 0xA Fast Time Constant A Exponent Reserved 0xA Fast Time Constant B Exponent Reserved 0x20 Fast Time Constant A Linear Reserved 0x20 Fast Time Constant B Linear Reserved 0x6 Slow Time Constant A Exponent Reserved 0x6 Slow Time Constant B Exponent Reserved 0x20 Slow Time Constant A Linear
LLK_PLL_TC_AEF
0x080B R/W
[7:4] [3:0] [7:4] R/W [3:0] [7:6] R/W [5:0] [7:6] R/W [5:0] [7:4] R/W [3:0] [7:4] R/W [3:0] [7:6] R/W [5:0]
LLK_PLL_TC_BEF
0x080C
LLK_PLL_TC_ALF
0x080D
LLK_PLL_TC_BLF
0x080E
LLK_PLL_TC_AES
0x080F
LLK_PLL_TC_BES
0x0810
LLK_PLL_TC_ALS
0x0811
20/88
ADE3XXX
Table 7: Line Lock PLL Registers (Sheet 3 of 4) Register Name
LLK_PLL_TC_BLS
Line Lock PLL Block
Addr
0x0812
Mode
Bits
[7:6]
Default
Reserved 0x20
Description
R/W LLK_PLL_TC_AEK 0x0813 R/W LLK_PLL_TC_BEK 0x0814 R/W LLK_PLL_TC_ALK 0x0815 R/W LLK_PLL_TC_BLK 0x0816 R/W LLK_PLL_TC_SLOW_TOL 0x0817 R/W
[5:0] [7:4] [3:0] [7:4] [3:0] [7:6] [5:0] [7:6] [5:0] [7:0]
Slow Time Constant B Linear Reserved
0x6
Lock Time Constant A Exponent Reserved
0x6
Lock Time Constant B Exponent Reserved
0x20
Lock Time Constant A Linear Reserved
0x20 0x80
Lock Time Constant B Linear More than SLOW_LINE_NB lines with a phase error less than the SLOW_TOL will set the slow status bit, and the PLL will work with the slow time constant. One or more lines with a phase error more than SLOW_TOL will reset the slow status bit, and the PLL will work with the fast time constant. LSB of SLOW_TOL is approx. 200ps.
LLK_PLL_TC_SLOW_LINE_NB LLK_PLL_LOCK_TOL
0x0818 0x0819
R/W R/W
[7:0] [7:0]
0x10 0x20 More than LOCK_LINE_NB lines with a phase error less than the LOCK_TOL will set the lock status bit, and the PLL will work with the lock time constant. One or more lines with a phase error more than LOCK_TOL will reset the lock status bit, and the PLL will work with the slow time constant. LSB of LOCK_TOL is approx. 200 ps.
LLK_PLL_LOCK_LINE_NB LLK_PLL_PH_OFFSET
0x081A 0x081B
R/W R/W
[7:0] [7:0]
0x30 0x0 Phase Adjustment. The maximum phase offset value is equal to PHASE_RATE[31:21] or 0x40, whichever is higher.
LLK_PLL_PH_OFFSET_EN
0x081C
R/W
[7] [6:0]
0x0
Phase Enable Reserved
LLK_PLL_PULSE_HIGH_EXT
0x081D
R/W
[7] [6:3]
0x0
0: no pulse extend 1: extend pulse (normal) Reserved
R/W
[2:0]
0x0
Pulse Extend Amount 0x0: Minimum 0x7: Maximum (Normal)
LLK_PLL_STAT_LINES_L LLK_PLL_STAT_LINES_H LLK_PLL_STAT_ERROR_INC_LOW
0x081E 0x081F 0x0820
R/W R/W
[7:0] [7:0] [7:0]
0x10
Number of lines to statistically analyze.
Reserved
21/88
Digital Video Input (DVI)
Table 7: Line Lock PLL Registers (Sheet 4 of 4) Register Name
LLK_PLL_UPDATE
ADE3XXX
Addr
0x0840
Mode
R
Bits
[7]
Default
Description
In Free-running mode, toggles when status is updated. In one-shot mode, this bit is set when status is ready.
[6:2] R/W R/W LLK_PLL_STATUS 0x0841 R R R R LLK_PLL_PH_ERROR_L LLK_PLL_PH_ERROR_H LLK_PLL_PHASE_RATE_0 LLK_PLL_PHASE_RATE_1 LLK_PLL_PHASE_RATE_2 LLK_PLL_PHASE_RATE_3 LLK_PLL_PHASE_RATE_I_0 LLK_PLL_PHASE_RATE_I_1 LLK_PLL_PHASE_RATE_I_2 LLK_PLL_PHASE_RATE_I_3 LLK_PLL_STAT_ERROR_MEAN LLK_PLL_STAT_ERROR_PP_L LLK_PLL_STAT_ERROR_PP_H LLK_PLL_STAT_ERROR_ABS_L 0x0842 0x0843 0x0844 0x0845 0x0846 0x0847 0x0848 0x0849 0x084A 0x084B 0x084C 0x084D 0x084E 0x084F R R R R R R R R R R R R R R [1] [0] [7:4] [3] [2] [1] [0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] 0x0 0x0
Reserved 0: Free-running mode 1: one-shot mode update enable Reserved LLK overflow coarse error = 0 in slow mode in lock mode phase error LSB = approx. 200ps LLK phase rate fOUT = fXTAL x 227+NDIV / PHASE_RATE
integral phase rate
Average Phase Error over STAT_LINES phase error LSB is approx. 200ps Peak Phase Error over STAT_LINES phase error LSB is approx. 200ps sum of absolute phase errors over STAT_LINES phase error LSB is approx. 200ps
LLK_PLL_STAT_ERROR_ABS_H LLK_PLL_STAT_ERROR_GTX
0x0850 0x0851
R
[7:0] [7:0] Reserved
2.5
Digital Video Input (DVI)
The DVI receiver has the following features:
q q q q q
compatible with all DVI complaint transmitters up to 140 MHz pixel clock on chip termination adjustable by I2C and/or one (~10X) external reference resistor HDCP and standby / power down supported decoder digitally corrects for skew errors of at least 1 pixel in reference to any other channel bitstream can be decoded and measured without the presence of horizontal and vertical sync pulses
22/88
ADE3XXX
Digital Video Input (DVI)
Recommended values for best receiver quality are given in the following table:
Table 8: Recommended DVI Values Clock Speed
0 to 30 MHz 31 to 60 MHz 61 to 100 MHz 101 to 140 MHz
DVI_PLL_0
0x02 0x03 0x04 0x05
DVI_PLL_1
0x00 0x00 0x00 0x00
Table 9: DVI Registers (Sheet 1 of 5) Register Name
DVI_ACCUM_CONST
Addr
0x0401
Mode
Bits
[7:4]
Default
0x5 0x5 Reserved
Description
R/W
[3:0]
digital filter response speed 5: fastest 14: slowest
DVI_EXT_SHIFT_CNT
0x0402
R/W R/W
[7:6] [5:0] [7:6] 0x08
Reserved alignment position of chan0, used for debugging only Reserved 0x0 0x0 0: normal 1: freeze alignment readout initial value for the alignment position for all channels invalid code count for left position.
DVI_EXT_SHIFT_CNT_ENAB
0x0403 R/W R/W
[6] [5:0]
DVI_INVALID_L
0x0404 R R [7:3] [2:0] 0x0 0x0
exponent mantissa count = (mant+8) * 2(exp-4), if exp>3, else count = mant
DVI_INVALID_C
0x0405 R R [7:3] [2:0] 0x0 0x0
invalid code count for center position. exponent mantissa count = (mant+8) * 2(exp-4), if exp>3, else count = mant
DVI_INVALID_R
0x0406 R R [7:3] [2:0] 0x0 0x0
invalid code count for right position. exponent mantissa count = (mant+8) * 2(exp-4), if exp>3, else count = mant
23/88
Digital Video Input (DVI)
Table 9: DVI Registers (Sheet 2 of 5) Register Name
DVI_INVALID_SEL_EN
ADE3XXX
Addr
0x0407
Mode
R/W R/W
Bits
[7:3] [2:1]
Default
Reserved 0x0
Description
channel to count invalid code events 0: blue channel 1: green channel 2: red channel
R/W
[0]
0x0
invalid code accumulation period 0: 16k lines 1: 4 lines
DVI_ERROR_SKEW_EN
0x0408
R/W R/W R/W R/W
[7:3] [2] [1] [0] [7:4] [3:0] [7:4] [3:0] [7:0] [3:0] [7:0] [3:0] [7] [6] [5] [4] [3] [2] [1] [0] [7:0]
0x0 0x0 0x0 0x0 0x7 0x4 0x0 0x0 0x0 0x9 0xF 0x0 0x1 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
Reserved 0: tracking in data & blanking 1: tracking only in blanking enable channel skew protection enable error concealment 4 bit incr value (2's complement) 4 bit incr value (2's complement) 4 bit incr value (2's complement) 4 bit incr value (2's complement) 4 bit incr value (2's complement) 4 bit incr value (2's complement) 4 bit incr value (2's complement) 4 bit incr value (2's complement) Enable Restoring Force for LCR7. Enable Restoring Force for LCR6. Enable Restoring Force for LCR5. Enable Restoring Force for LCR4. Enable Restoring Force for LCR3. Enable Restoring Force for LCR2. Enable Restoring Force for LCR1. Enable Restoring Force for LCR0. Reserved Termination control 0: 50ohm Impedance (normal) 1: High impedance
DVI_LCR0_1
0x0409
R/W R/W
DVI_LCR2_3
0x040A
R/W R/W
DVI_LCR4_5
0x040B
R/W R/W
DVI_LCR6_7
0x040C
R/W R/W
DVI_LCR_RV_EN
0x040D
R/W R/W R/W R/W R/W R/W R/W R/W
DVI_TEST_SEL DVI_PLL_0
0x040E 0x0480 R/W
[7]
24/88
ADE3XXX
Table 9: DVI Registers (Sheet 3 of 5) Register Name
DVI_PLL_0
Digital Video Input (DVI)
Addr
0x0480
Mode
R/W R/W
Bits
[7] [6:5]
Default
Description
Reserved, must be set to 0
0x0
Amplifier Current 0x0: 25uA (default) 0x1: 75uA 0x2: 125uA 0x3: 175uA (fastest)
R/W
[4:3]
0x0
VTOL Range Overlap 0x0: 34.1uA (default) 0x1: 50.9uA 0x2: 26.0uA 0x3: 42.9uA
R/W
[2:0]
0x0
Change Pump Current Select 0x0: 25uA (default) 0x1: 50uA 0x2: 75uA 0x3: 100uA 0x4: 125uA 0x5: 150uA 0x6: 175uA 0x7: 200uA (fastest)
DVI_PLL_1
0x0481
R/W
[7]
0x0
Bias Select 0: internal (default) 1: external
R/W
[6:5]
0x0
Range Checking Interval 0x0: CLK/512 (default) 0x1: CLK/1024 0x2: CLK/2048 0x3: CLK/256
R/W
[4:1]
0x0
Manual Range Select 0x0: Reserved 0x1: force Range 1 (lowest) 0x2 - 0x3: force Range 2 0x4 - 0x7: force Range 3 0x8 - 0xF: force Range 4 (highest)
[0]
0x0
PLL Range Control 0: Auto (Default) 1: Manual
DVI_PLL_2
0x0482
R/W
[7:6]
0x0
Strobe 3 Adjust 0: Normal 1: Slower 2: Faster 3: Reserved
R/W R/W R/W
[5:4] [3:2] [1:0]
0x0 0x0 0x0
Strobe 2 Adjust Strobe 1 Adjust Global Strobe Adjust 0: Normal 1: Slower 2: Faster 3: Reserved
25/88
Digital Video Input (DVI)
Table 9: DVI Registers (Sheet 4 of 5) Register Name
DVI_PLL_3
ADE3XXX
Addr
0x0483
Mode
R/W R/W R/W R/W
Bits
[7:6] [5:4] [3:2] [1:0] [7:6] [5:4] [3:2] [1:0] [7:6] [5:4] [3:2] [1:0] [7:6] [5:4] [3:2] [1:0] [7:6] [5:4] [3:2] [1:0] [7:6] [5:4] [3:2] [1:0] [7:6] [5:4] [3:2] [1:0]
Default
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Strobe 7 Adjust Strobe 6 Adjust Strobe 5 Adjust Strobe 4 Adjust
Description
DVI_PLL_4
0x0484
R/W R/W R/W R/W
Strobe 11 Adjust Strobe 10 Adjust Strobe 9 Adjust Strobe 8 Adjust Strobe 15 Adjust Strobe 14 Adjust Strobe 13 Adjust Strobe 12 Adjust Strobe 19 Adjust Strobe 18 Adjust Strobe 17 Adjust Strobe 16 Adjust Strobe 23 Adjust Strobe 22 Adjust Strobe 21 Adjust Strobe 20 Adjust Strobe 27 Adjust Strobe 26 Adjust Strobe 25 Adjust Strobe 24 Adjust Strobe [0:3] Delay Adjustment 0x0: Normal 0x1: Slow 0x2: Fast 0x3: Reserved
DVI_PLL_5
0x0485
R/W R/W R/W R/W
DVI_PLL_6
0x0486
R/W R/W R/W R/W
DVI_PLL_7
0x0487
R/W R/W R/W R/W
DVI_PLL_8
0x0488
R/W R/W R/W R/W
DVI_PLL_2
0x0482
R/W
DVI_PLL_3
0x0483
R/W
[7:6] [5:4] [3:2] [1:0]
0x0
Strobe [4:7] Delay Adjustment 0x0: Normal 0x1: Slow 0x2: Fast 0x3: Reserved
DVI_PLL_4
0x0484
R/W
[7:6] [5:4] [3:2] [1:0]
0x0
Strobe [8:11] Delay Adjustment 0x0: Normal 0x1: Slow 0x2: Fast 0x3: Reserved
DVI_PLL_5
0x0485
R/W
[7:6] [5:4] [3:2] [1:0]
0x0
Strobe [12:15] Delay Adjustment 0x0: Normal 0x1: Slow 0x2: Fast 0x3: Reserved
26/88
ADE3XXX
Table 9: DVI Registers (Sheet 5 of 5) Register Name
DVI_PLL_6
HDCP Block
Addr
0x0486
Mode
R/W
Bits
[7:6] [5:4] [3:2] [1:0]
Default
0x0
Description
Strobe [16:19] Delay Adjustment 0x0: Normal 0x1: Slow 0x2: Fast 0x3: Reserved
DVI_PLL_7
0x0487
R/W
[7:6] [5:4] [3:2] [1:0]
0x0
Strobe [20:23] Delay Adjustment 0x0: Normal 0x1: Slow 0x2: Fast 0x3: Reserved
DVI_PLL_8
0x0488
R/W
[7:6] [5:4] [3:2] [1:0]
0x0
Strobe [24:27] Delay Adjustment 0x0: Normal 0x1: Slow 0x2: Fast 0x3: Reserved Reserved
DVI_PLL_9
0x0489 R/W R/W
[7:6] [5] [4] 0x0 0x0
Test Enable (normal operation = 0) Strobe Delay Adjustment Step 0: 45pS (default) 1: 72pS
R/W
[3:2]
0x0
Strobe 29 Adjust 0: Normal 1: Slower 2: Faster 3: Reserved
R/W R/W
[1:0] [3:2] [1:0]
0x0 0x0
Strobe 28 Adjust Strobe [28:29] Delay Adjustment 0x0: Normal 0x1: Slow 0x2: Fast 0x3: Reserved Reserved Test Output DVIPLL[79:77] PLL Range Status
DVI_PLL_10
0x048A R R R
[7] [6:4] [3:0] [3:0] 0x0
PLL Range Status
2.6
HDCP Block
The HDCP block implements the datapath decryption block of the HDCP content protection scheme of DVI. Please refer to the HDCP Specification 1.0 for details. The state machines of the HDCP specification are split between the external microcontroller and this block. Only the high speed and data intensive cryptographic functions are implemented in this block to maintain maximum system level flexibility.
27/88
HDCP Block
ADE3XXX
Table 10: HDCP Registers Register Name
HDCP_STATUS
Addr
0x0500
Mode
Bits
[7:3]
Default
0x0 0x0 Reserved
Description
R
[2:0]
Decrypt State Machine 0x0: Idle 0x1: Frame Key Recalc 0x2: Data 0x3: Unknown Blank 0x4: Horizontal Blank 0x5: Vertical Blank 0x6-0x7: Reserved
HDCP_CTRL
0x0501
R/W
[7:6]
0x0
Vsync Selection 0x0: IN_VSYNC 0x1: IN_VENAB Falling Edge 0x2: IN_VENAB Rising Edge 0x3: IN_VSYNC Falling Edge
R/W
[5:4]
0x0
Hsync Selection 0x0: IN_HSYNC 0x1: IN_ENAB Falling Edge 0x2: IN_ENAB Rising Edge 0x3: IN_HSYNC Falling Edge
R/W R/W R/W HDCP_AN0 HDCP_AN1 HDCP_AN2 HDCP_AN3 HDCP_AN4 HDCP_AN5 HDCP_AN6 HDCP_AN7 HDCP_KM0 HDCP_KM1 HDCP_KM2 HDCP_KM3 HDCP_KM4 HDCP_KM5 HDCP_KM6 HDCP_R_L HDCP_R_H 0x0502 0x0503 0x0504 0x0505 0x0506 0x0507 0x0508 0x0509 0x050A 0x050B 0x050C 0x050D 0x050E 0x050F 0x0510 0x0511 0x0512 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
[2] [1] [0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0]
0x0 0x0 0x0 0x0
Bypass HDCP block Authentication OK from MCU 0: State Machine Standby 1: Trigger an Authentication Cycle An
0x0
Kn
0x0
R
28/88
ADE3XXX
YUV Block
2.7
YUV Block
The TV video input module is used to interface external TV video decoder chip. It handles VESA Video Interface Port(VIP) 8-bit/16-bit YCBCR, VMI/ ITU-R Recommendation 656 (CCIR656) YCBC R and double clock edge input RGB data formats. It extracts embedded sync timing and converts data into RGB color space. All the functions in this module are controlled by the system microcontroller through I2C registers. The following table describes the different pin configurations for YUV/RGB digital input.
Mode
CCIR656 VMI VIP 8b VIP 16b RGB Posedge RGB Negedge
YUV[7:0]
DATA[7:0] DATA[7:0] DATA[7:0] DATA[7:0] BLUE[7:0] {RED[3:0],GREEN[7:4]}
TCON[3:0]
X X X DATA[11:8] GREEN[3:0] RED[7:4]
TCON[7:4]
X {HREF, VREF, VACTIVE, X} X DATA[15:12] {HSYNC,VSYNC,DE,X} {HSYNC,VSYNC,DE,X}
X = don't care
Table 11: YUV Registers (Sheet 1 of 2) Register Name
YUV_CTRL
Addr
0x0700
Mode
Bits
[7:6]
Default
Reserved 0x0 0x0
Description
R/W R/W
[5] [4]
0: Rising edge of clock 1: Falling edge of clock Input Source of Color Space Converter 0: YUV pins 1: ADC
R/W R/W R/W
[3] [2] [1]
0x0 0x0 0x0
Color Space Converter Enable Sync Decoder Enable Sample Input Data Rate 0:1x 1: 2x
R/W YUV_STATUS 0x0701 R/W R/W R/W R/W R/W R/W R/W
[0] [7] [6] [5] [4] [3] [2] [1] [0]
0x0
Status Reset Reserved
0x0 0x0 0x0 0x0 0x0 0x0 0x0
SAV detected EAV detected ANC detected TASK detected FIELDID detected HSYNC detected VSYNC detected Writing to this register will clear all bits.
29/88
Sync Retiming Block
Table 11: YUV Registers (Sheet 2 of 2) Register Name
YUV_INT
ADE3XXX
Addr
0x0702
Mode
Bits
[7:6]
Default
Reserved 0x0
Description
R/W
[5]
0: VIP 8b mode 1: VIP 16b mode (skip 1 clock after every 6 valid data) YUV data input format 0x2: YUV 16-bit 0x4: YUV 8-bit 0x6: RGB all others: Reserved
R/W
[4:2]
0x0
R/W R/W
[1] [0]
0x0 0x0
0: C-Y 1: Y-C 0: Cr-Cb 1: Cb-Cr
2.8
Sync Retiming Block
The Sync Retiming (SRT) block retimes incoming synchronization signals (H Sync, V Sync, etc) into the XCLK and INCLK domains. For the XCLK domain, SRT has the following functionality:
q q q q q
Retimes all sync signals going to SMEAS into the XCLK domain. Extracts vertical sync from composite sync signals (ahsync and acsync pins) Divides clocks by 1024 for activity detection purposes. Generates a delay-filtered version of vertical sync from a mux-selectable vertical sync source. Generates a coast signal in the XCLK domain for the LLPLL.
Table 12: Sync Retiming Registers (Sheet 1 of 2)
Register Name
SRTXK_CSYNC_INV
Addr
0x01E0
Mode
Bits
[7:3]
Default
0x0 0x0 0x0 0x0 0x080 Reserved
Description
R/W R/W R/W SRTXK_SOG_THR_L SRTXK_SOG_THR_H 0x01E1 0x01E2 R/W R/W
[2] [1] [0] [7:0] [7:4] [3:0]
invert filtered vert sync signal invert composite sync signal invert SOG signal SOG vert sync extractor threshold [7:0] Reserved SOG vert sync extractor threshold [11:8]
SRTXK_CSYNC_THR_L SRTXK_CSYNC_THR_H
0x01E3 0x01E4
R/W R/W
[7:0] [7:4] [3:0]
0x080
composite sync vertical sync extractor threshold [7:0] Reserved composite sync vertical sync extractor threshold [11:8]
30/88
ADE3XXX
Table 12: Sync Retiming Registers (Sheet 2 of 2) Register Name
SRTXK_VSYNC_SEL
Sync Retiming Block
Addr
0x01E5
Mode
R/W
Bits
[7:3] [2:0]
Default
Reserved 0x0
Description
filtered vert sync source select 0x0: avsync pin 0x1: vsync from composite ahsync pin 0x2: vsync from composite acsync pin 0x3: Reserved 0x4: DVI vsync 0x5: YUV vsync 0x6 - 0x7: Reserved
SRTXK_VSYNC_THR_L SRTXK_VSYNC_THR_H
0x01E6 0x01E7
R/W R/W R/W
[7:0] [7:4] [3:0] [7:4]
0x080
filtered vert sync delay [7:0] Reserved filtered vert sync delay [11:8]
SRTXK_COAST_VS_SEL
0x01E8 R/W
0x0 0x0
Reserved coast signal trigger edge 0: posedge of selected vertical 1: negedge of selected vertical source select for coast vert sync trigger 0x0: avsync pin 0x1: vsync from ahsync pin 0x2: vsync from acsync pin 0x3: Reserved 0x4: DVI vsync 0x5: YUV vsync 0x6: srt vsync (filtered vsync) 0x7: Reserved
[3]
R/W
[2:0]
0x0
SRTXK_COAST_RISE_L SRTXK_COAST_RISE_M SRTXK_COAST_RISE_H SRTXK_COAST_FALL_L SRTXK_COAST_FALL_M SRTXK_COAST_FALL_H SRTIK_HS_CTRL
0x01E9 0x01EA 0x01EB 0x01EC 0x01ED 0x01EE 0x01F0
R/W R/W R/W R/W R/W R/W
[7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:3]
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
rising edge of coast, in XCLKs from vsync trigger
falling edge of coast, in XCLKs from vsync trigger
Reserved Resample clock edge to transfer hsync into the INCLK domain; depends on LLK phase offset value. 0: posedge INCLK 1: negedge INCLK
R/W
[2]
R/W
[1:0]
0x0
horz sync source select for resampling into the INCLK domain 0x0: LLPLL lock sync (normal) 0x1: ahsync pin 0x2: acsync pin 0x3: Reserved
SRTIK_VS_SEL
0x01F1 R/W
[7:2] [1:0]
0x0 0x0
Reserved vert sync source select for resampling 0x0: avsync pin 0x1: vsync from ahsync pin 0x2: vsync from acsync pin 0x3: srt vsync (filtered vsync)
31/88
Sync Measurement Block
ADE3XXX
2.9
Sync Measurement Block
The Input Sync Measurement Block (SMEAS) continuously detects activity from all video sources. The module can measure the characteristics of the sync signals on any input port. The sync measurement module reports the results of the measurements to the system microcontroller. This portion of the sync measurement is fully synchronous on the crystal clock (XCLK). Another block, the Sync Retiming Block (SRT), handles the asynchronous signal transfer of the incoming sync signals. Input Sync Functions:
q q q
Activity detection Sync management Measurement
Table 13: Sync Measurement Registers (Sheet 1 of 8)
Register Name
SMEAS_ACT_CTRL
Addr
0x0100
Mode
Bits
[7:4]
Default
0x0 0x0 0x0 Reserved
Description
R/W R/W
[3] [2]
Enable activity detection in Free-running mode. Freeze results in Free-running mode. No meaning in One-shot mode. 0: Do not freeze the results. New result will be available on the next and subsequent toggle of the polling bit. 1: Freeze the current results. The polling bit will still toggle and the block continues to free run; however, results will not be updated.
R/W
[1]
0x0
activity detection start. In one-shot mode it triggers the start of a measurement and is reset to zero when the measurement is complete.
R/W
[0]
0x0
activity detection mode control 0: free run 1: one shot
SMEAS_ACT_H_SMPTM_L SMEAS_ACT_H_SMPTM_H SMEAS_ACT_V_SMPTM_L SMEAS_ACT_V_SMPTM_H
0x0101 0x0102 0x0103 0x0104
R/W R/W R/W R/W
[7:0] [7:0] [7:0] [7:0]
0x0 0x0 0x0 0x0
Sample time value for clock or hsync activity. In units of XCLK_period*256 Sample time value for vsync activity in units of XCLK_period*256. Note: this number MUST be larger than hsync sample time.
SMEAS_ACT_H_MINEDGE SMEAS_ACT_V_MINEDGE SMEAS_H_TMOT_L SMEAS_H_TMOT_H SMEAS_V_TMOT_L SMEAS_V_TMOT_H
0x0105 0x0106 0x0107 0x0108 0x0109 0x010A
R/W R/W R/W R/W R/W R/W
[7:0] [7:0] [7:0] [7:0] [7:0] [7:0]
0x0 0x0 0x4000
Minimum edge count value for clk or hsync activity. Minimum edge count value for vsync activity. timeout counter value for clk or horizontal measurement in XCLKs timeout counter value for vertical measurement in units of XCLK/256
0x1600
32/88
ADE3XXX
Sync Measurement Block
Table 13: Sync Measurement Registers (Sheet 2 of 8)
Register Name
SMEAS_CLEAR
Addr
0x0110
Mode
Bits Default
[7:3] Reserved 0x0 0x0 0x0 0x0 0x0
Description
R/W R/W R/W SMEAS_H_CTRL 0x0111 R/W
[2] [1] [0] [7] [6]
clear sticky status bits clear all out-of-range event counters clear all result registers Reserved Enable Hsync Filter All hsync pulses less than SMEAS_FILTER_HS_WIDTH will be ignored.
R/W R/W R/W
[5] [4] [3]
0x0 0x0 0x0
Measure hsync in the absence of vsync Enable Horizontal Measurement in Freerunning mode Horizontal Event Edge Select 0: positive edge 1: negative edge
R/W
[2]
0x0
Freeze horizontal measurements results during Free-running mode. No meaning in One-shot mode. 0: Do not freeze measurement results. New result will be available on the next and subsequent toggle of the polling bit. 1: Freeze the current results. The polling bit will still toggle and the block continues to free run; however, results will not be updated.
R/W
[1]
0x0
Horizontal Measurement Start In one-shot mode, this bit triggers the start of a measurement. The bit is reset to zero when the measurement is complete.
R/W
[0]
0x0
Horizontal Measurement Mode 0: Free-running 1: One-shot
33/88
Sync Measurement Block
Table 13: Sync Measurement Registers (Sheet 3 of 8) Register Name
SMEAS_V_CTRL
ADE3XXX
Addr
0x0112
Mode
Bits
[7]
Default
0x0 0x0 0x0 Reserved
Description
R/W R/W
[6] [5]
Enable Interlace Measurement Measure odd frame from YUV only. Applies only if the odd signal from YUV is present. The results in SMEAS_XCLKS_PER_H and SMEAS_H_PER_V are updated for odd frames if this bit is set. Enable Vertical Measurement in Freerunning mode. Vertical Event Edge select 0: positive edge 1: negative edge
R/W R/W
[4] [3]
0x0 0x0
R/W
[2]
0x0
Freeze Vertical Measurement results in Free-running mode. No meaning in One-shot mode. 0: Do not freeze the results. New result will be available on the next and subsequent toggle of the polling bit. 1: Freeze the current results in Free-running mode. The polling bit will still toggle and the block continues to free run; however, results will not be updated.
R/W
[1]
0x0
Vertical measurement start. In One-shot mode, this bit triggers the start of a measurement. The bit is reset to zero when the measurement is complete.
R/W
[0]
0x0
Vertical measurement mode 0: Free-running 1: One-shot
SMEAS_H_SEL
0x0113
R/W
[7:4] [3:0] 0x0
Reserved Select a horizontal sync, enable or clock for measurement. 0x0: Analog hsync 0x1: Hsync generated from LLPLL 0x2: SOG from csync pin 0x3: DVI hsync 0x4: YUV hsync 0x5: DVI data enable 0x6: YUV data enable 0x7: DVIclk div1k 0x8: YUVclk div1k 0x9: TCON hsync 0xA: TCON data enable 0xB: INCLK div1k 0xC: DOTCLK div1k 0xD-0xF: Reserved
34/88
ADE3XXX
Sync Measurement Block
Table 13: Sync Measurement Registers (Sheet 4 of 8)
Register Name
SMEAS_V_SEL
Addr
0x0114
Mode
R/W
Bits Default
[7:4] 0x0
Description
Selects a vertical signal for measurement of the high pulse width. 0x0: Analog vsync 0x1: Composite vsync 0x2: SOG vsync 0x3: DVI vsync 0x4: YUV vsync 0x5: YUV vert enab (locally generated) 0x6: DVI vert enab (locally generated) 0x7: TCON vsync 0x8 - 0xF: Reserved
R/W
[3:0]
0x0
Selects a vertical signal for measurement of period and polarity. 0x0: Analog vsync 0x1: Composite vsync 0x2: SOG vsync 0x3: DVI vsync 0x4: YUV vsync 0x5: YUV vert enable (locally generated) 0x6: DVI vert enable (locally generated) 0x7: TCON vsync
SMEAS_STATUS_MASK
0x0119
R/W
[7]
0x0
Mask bit for hsync polarity check 0: ignore 1: check
R/W
[6]
0x0
Mask bit for vsync polarity check 0: ignore 1: check
[5:4] R/W [3] 0x0
Reserved Mask bit for vert pulse width check 0: ignore 1: check
R/W
[2]
0x0
Mask bit for h per v check 0: ignore 1: check
R/W
[1]
0x0
Mask bit for h period check 0: ignore 1: check
R/W
[0]
0x0
Mask bit for v period check 0: ignore 1: check
SMEAS_H_NUM_LINES SMEAS_H_SKIP_L
0x011A 0x011B
R/W R/W
[7:0] [7:0]
0x0 0x0
Number of lines to measure for Horizontal period. Valid range is 1 to 255. Number of lines to skip before starting a horizontal measurement. The skip counter counts from the chosen vertical source and edge. [7:0] Reserved Number of lines to skip before starting a horizontal measurement. The skip counter counts from the chosen vertical source and edge. [11:8]
SMEAS_H_SKIP_H
0x011C
R/W
[7:4] [3:0]
35/88
Sync Measurement Block
Table 13: Sync Measurement Registers (Sheet 5 of 8) Register Name
SMEAS_SKEW_CTRL
ADE3XXX
Addr
0x011D
Mode
Bits
[7:3]
Default
0x0 0x0 0x0 0x0 0x5 Reserved
Description
R/W
[2] [1]
1 = delay vsync a number of XCLKs specified in SMEAS_DELAY_VSYNC Reserved Write a rising edge to start the hv-skew measurement. Test skew limit in XCLKs. If the skew is less than this test limit, the SMEASE_SKEW_STATUS register will report an error condition. SMEAS_DELAY_VSYNC should be reprogrammed until the skew is large enough to prevent vcount ambiguity. Number of XCLKs to delay vsync. Reference value for XCLKs per horizontal event actual value = programmed value + 1 Reference value for XCLKs per vertical event actual value = programmed value + 2 Reference value for horizontal events per vertical event Reference value for vertical pulse width measurement result in XCLKs. actual value = programmed value + 1 Reserved Reference value for Hsync polarity. 0: active low 1: active high
R/W SMEAS_SKEW_THRES 0x011E R
[0] [7:0]
SMEAS_DELAY_VSYNC SMEAS_REF_XK_PER_H_L SMEAS_REF_XK_PER_H_M SMEAS_REF_XK_PER_H_H SMEAS_REF_XK_PER_V_L SMEAS_REF_XK_PER_V_M SMEAS_REF_XK_PER_V_H SMEAS_REF_H_PER_V_L SMEAS_REF_H_PER_V_H SMEAS_REF_XK_V_PER_HI_L SMEAS_REF_XK_V_PER_HI_M SMEAS_REF_XK_V_PER_HI_H SMEAS_REF_POLARITY
0x011F 0x0120 0x0121 0x0122 0x0123 0x0124 0x0125 0x0126 0x0127 0x0128 0x0129 0x012A 0x012B
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
[7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:2]
0x3 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
R/W
[1]
R/W
[0]
0x0
Reference value for Vsync polarity. 0: active low 1: active high
SMEAS_XK_HTOL_EXP
0x012C
R/W
[7:4] [3:0]
0x0 0x0 0x0 0x0 0x0 0x0 0x1 0x0 0x0
Reserved Horizontal tolerance; +/- 2n XCLKs Reserved Vertical tolerance; +/- 2n XCLKs Reserved Horizontal per vertical tolerance, +/- 2n Refer to register 0x0111 Reserved Toggle on activity status update in Freerunning mode. No function in one-shot mode.
SMEAS_XK_VTOL_EXP
0x012D R/W
[7:4] [3:0] [7:4] R/W [3:0] [7:0] [7:1] R [0]
SMEAS_HSYNC_VTOL
0x012E
SMEAS_FILTR_HS_WIDTH SMEAS_ACT_POLLING
0x012F 0x013F
R/W
36/88
ADE3XXX
Sync Measurement Block
Table 13: Sync Measurement Registers (Sheet 6 of 8)
Register Name
SMEAS_ANA_ACT
Addr
0x0140
Mode
Bits Default
[7:5] 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Reserved
Description
R R R R R SMEAS_DVI_ACT 0x0141 R R SMEAS_YUV_ACT 0x0142 R R R R R SMEAS_ANA_STUCK 0x0143 R R R R R SMEAS_DVI_STUCK 0x0144 R R SMEAS_YUV_STUCK 0x0145 R R R R R R SMEAS_XK_PER_H_L SMEAS_XK_PER_H_M SMEAS_XK_PER_H_H SMEAS_XK_PER_V_L SMEAS_XK_PER_V_M SMEAS_XK_PER_V_H 0x0146 0x0147 0x0148 0x0149 0x014A 0x014B R R R R R R
[4] [3] [2] [1] [0] [7:2] [1] [0] [7:5] [4] [3] [2] [1] [0] [7:5] [4] [3] [2] [1] [0] [7:2] [1] [0] [7:5] [4] [3] [2] [1] [0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0]
Composite sync is active Vsync from SOG separator is active Comp vsync from composite sync separator is active Analog hsync is active Analog vsync is active Reserved DVI enable is active DVI clk / 1K is active Reserved TCON vsync is active. TCON hsync is active. TCON enable is active. YUV enable is active. YUV clk / 1K is active. Reserved Comp sync is stuck at 1(high)/0(low) Vsync from SOG separator is stuck at 1(high)/0(low) Comp vsync from separator is stuck at 1(high)/0(low) Analog hsync is stuck at 1(high)/0(low) Analog vsync is stuck at 1(high)/0(low) Reserved DVI data enable is stuck at 1(high)/0(low) DVI clk / 1K is stuck at 1(high)/0(low) Reserved TCON vsync is stuck at 1(high)/0(low) TCON hsync is stuck at 1(high)/0(low) TCON data enable is stuck at 1(high)/0(low) YUV data enable is stuck at 1(high)/0(low) YUV clk / 1K is stuck at 1(high)/0(low) XCLKs per horizontal event - 1
XCLKs per vertical event - 1
37/88
Sync Measurement Block
Table 13: Sync Measurement Registers (Sheet 7 of 8) Register Name
SMEAS_H_PER_V_L SMEAS_H_PER_V_H SMEAS_SK_V_HI_L SMEAS_SK_V_HI_M SMEAS_SK_V_HI_H SMEAS_TIMEOUT_STATUS
ADE3XXX
Addr
0x014C 0x014D 0x014E 0x014F 0x0150 0x0151
Mode
R R R R R
Bits
[7:0] [7:0] [7:0] [7:0] [7:0] [7:2]
Default
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Reserved
Description
Horizontal events per vertical event
Vertical high time in XCLKs - 1
R R SMEAS_STATUS_RANGE 0x0152 R
[1] [0] [7]
Indicates that the horizontal measurement timed out. Indicates that the vertical measurement timed out. In Free-running mode any of the status bits can change at the end of each measurement. In One-shot mode any of the status bits can change at the completion of the measurement. The meas_sticky_status bit is a bitwise OR of bits[3:0] (before the bitwise OR, the mask in SMEAS_STATUS_MASK is AND in) and is sticky. The only way to reset it is for software to write a zero into this bit. This bit goes to the scaler to blank the scaler output. A write to this reg will reset it to 0. Indicates that one of the measured polarities does not match the reference value. Hsync (selected by SMEAS_H_SEL) polarity. 0: active low 1: active high
R R
[6] [5]
0x0 0x0
R
[4]
0x0
Vsync (selected by SMEAS_V_SEL) polarity. 0: active low 1: active high
R
[3]
0x0
Indicates that the vertical pulse width measurement exceeded the reference +/tolerance range. Indicates that the horizontal per vertical measurement exceeded the reference +/tolerance range. Indicates that the XCLKs per horizontal measurement exceeded the reference +/tolerance range. Indicates that the XCLKs per vertical measurement exceeded the reference +/tolerance range. Reserved Toggle on h meas Free-running mode, at end of each meas. No function on one-shot mode. Toggle on v meas Free-running mode, at end of each meas. No function on one-shot mode.
R
[2]
0x0
R
[1]
0x0
R
[0]
0x0
SMEAS_MEAS_POLLING
0x0153 R
[7:2] [1]
0x0 0x0
R
[0]
0x0
38/88
ADE3XXX
Sync Measurement Block
Table 13: Sync Measurement Registers (Sheet 8 of 8)
Register Name
SMEAS_SKEW_STATUS
Addr
0x0154
Mode
Bits Default
[7:2] 0x0 0x0 0x0 0x0 Reserved
Description
R R SMEAS_V_OUTOF_RNG 0x0155 R
[1] [0] [7:0]
0: hsync to vsync skew above threshold 1: hsync to vsync skew below theshold 0: skew measurement running 1: skew measurement finished The number of times the XCLKs per vertical reference/meas comparison has been out of range. Maximum is 240. Clear by setting SMEAS_CLEAR[1]. The number of times the XCLKs per horizontal reference/meas comparison has been out of range. Maximum is 240. Clear by setting SMEAS_CLEAR[1]. The number of times the horizontal per vertical reference/meas comparison has been out of range. Maximum is 240. Clear by setting SMEAS_CLEAR[1]. The number of times the vertical pulse width in XCLKs reference/meas comparison has been out of range. Maximum is 240. Clear by setting SMEAS_CLEAR[1]. The number of times the horizontal polarity reference/meas comparison has been out of range. Maximum is 240. Clear by setting SMEAS_CLEAR[1]. The number of times the vertical polarity reference/meas comparison has been out of range. Maximum is 240. Clear by setting SMEAS_CLEAR[1].
SMEAS_H_OUTOF_RNG
0x0156
R
[7:0]
0x0
SMEAS_HV_OUTOF_RNG
0x0157
R
[7:0]
0x0
SMEAS_VHI_OUTOF_RNG
0x0158
R
[7:0]
0x0
SMEAS_HPOL_OUTOF_RNG
0x0159
R
[7:0]
0x0
SMEAS_VPOL_OUTOF_RNG
0x015A
R
[7:0]
0x0
39/88
Sync Mux Block
ADE3XXX
2.10
Sync Mux Block
The Sync Mux (SMUX) block provides the following functions:
q q q q
selects between all possible sync signals generates missing sync signals selects between original and generated signals for output generates the clamp signal for the ADC
Table 14: Sync Mux Registers (Sheet 1 of 2)
Register Name
SMUX_CTRL0
Addr
0x0200
Mode
R/W R/W R/W R/W
Bits
[7] [6] [5] [4]
Default
0x0 0x0 0x0 0x0
Description
Select TCON[7] as internal_hsync source. Overrides SMUX_CTRL0[1:0] selection. Select TCON[6] as internal_vsync source. Overrides SMUX_CTRL0[3:2] selection. Select TCON[5] as internal_enable source. Overrides SMUX_CTRL0[4] selection. Internal_enab select 0: DVI 1: YUV
R/W
[3:2]
0x0
Vsync_internal select 0x0: DVI 0x1: SRT vsync (normally analog) 0x2: YUVi 0x3: composite sync decoder
R/W
[1:0]
0x0
Hsync_internal select 0x0: DVI 0x1: LLK hsync (normally analog) 0x2: YUVi 0x3: raw vga hsync (may have jitter)
SMUX_CTRL1
0x0201 R/W R/W R/W
[7:6] [5] [4] [3]
0x0 0x0 0x0 0x0
Reserved Vsync_out invert Hsync_out invert V_reference edge select 0: falling 1: rising
R/W
[2]
0x0
V_reference select 0: venab_generated 1: vsync_internal
R/W
[1]
0x0
H_reference edge select 0: falling 1: rising
R/W
[0]
0x0
H_reference select 0: enab_internal 1: hsync_internal
40/88
ADE3XXX
Table 14: Sync Mux Registers (Sheet 2 of 2) Register Name
SMUX_CTRL2
Sync Mux Block
Addr
0x0202
Mode
R R/W R/W
Bits
[7] [6] [5:4]
Default
0x0 0x0 0x0
Description
V_reference toggle output Software odd set (for testing odd params on the bench) Odd_out select 0x0: YUV 0x1: v_reference toggle 0x2: SMUX_CTRL2[6] 0x3: Reserved Valid_out select 0: YUV 1: valid_generated Enab_out select 0: enab_internal 1: enab_generated Vsync_out select 0: vsync_internal 1: hsync_generated Hsync_out select 0: hsync_internal 1: hsync_generated ADC clamp signal rising edge [11:0], relative to selected horizontal reference signal, in INCLKs (pixels) ADC clamp falling edge [11:0]
R/W
[3]
0x0
R/W
[2]
0x0
R/W
[1]
0x0
R/W
[0]
0x0
SMUX_CLAMP_SET_L SMUX_CLAMP_SET_H SMUX_CLAMP_RST_L SMUX_CLAMP_RST_H SMUX_HENAB_SET_L SMUX_HENAB_SET_H SMUX_HENAB_RST_L SMUX_HENAB_RST_H SMUX_VENAB_SET_L SMUX_VENAB_SET_H SMUX_VENAB_RST_L SMUX_VENAB_RST_H SMUX_HSYNC_PHASE
0x0203 0x0204 0x0205 0x0206 0x0207 0x0208 0x0209 0x020A 0x020B 0x020C 0x020D 0x020E 0x020F
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
[7:0] [3:0] [7:0] [3:0] [7:0] [3:0] [7:0] [3:0] [7:0] [3:0] [7:0] [3:0] [7:0]
0x0 0x0 0x0 0x0 0x0 0x0 0x0
Horizontal enable start [11:0] (left edge of image) relative to the selected horizontal reference edge in INCLKs (pixels)) Horizontal enable end [11:0]
0x0 0x0 0x0 0x0 Vertical enable end 0x0 0x0 Number of horizontal pixels/INCLKs that the generated hsync edge is from the horizontal reference edge. 2's complement [-128,127] Number of vertical lines that the generated vsync edge is from the vertical reference edge. 2's complement [-128,127] Vertical enable start [11:0] (top edge of image) relative to the selected vertical reference edge (in lines)
SMUX_VSYNC_PHASE
0x0210
R/W
[7:0]
0x0
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Data Mux Block
ADE3XXX
2.11
Data Mux Block
Data mux provides the following functions:
q q
selection of one among three data sources debug modes (e.g. bit order swap, color swap)
Table 15: Data Mux Registers Register Addr.
0x0280 R/W R/W
Mode
Bits
[7] [6] [5:3]
Default
0x0 0x0 0x0 Reserved
Description
DMUX_CHANSEL
0: normal 1: msb/lsb byte flip If enabled by [2] 0x0: Reserved 0x1: R & G bytes are swapped 0x2: B & G bytes are swapped 0x3: R => G, G => B, B => R 0x4: R & B bytes are swapped 0x5: R => B, G => R, B => G 0x0, 0x6-0x7: Reserved
R/W R/W
[2] [1:0]
0x0 0x0
0: normal 1: enable color swap Video Source Select 0x0: ADC data 0x1: YUV data 0x2: DVI data 0x3: DVI xor YUV xor ADC (for test only)
2.12
Data Measurement Block
The Data Measurement module measures several characteristics of the data and sync signals. Data measurements are taken over a programmable window as defined by an upper left (mix_x, min_y) and a lower right (max_x, max_y), which may be the whole frame. Measurements are programmable either per color channel or over all color channels. This module computes all measurements of sync and data format that are done in the INCLK domain. The Sync Measurement module does measurements in the XCLK domain. The INCLKs per DE measurement does not use the window feature. It measures the number of INCLK per DE and returns the result for every line. All unused or reserved bits return as zero. Windows are relative to Sync pulses. A window defined from (0,0) - (0xFFF, 0xFFF) goes from sync to sync. The reference edge to use, rising or falling, is also programmable per X and Y coordinates. Configure SMUX to provide a positive polarity sync to the DMEAS block. All window enables reset at 0 and always reset on the rising or falling edge of sync. See the description of the specific PHM and DMM measurements performed within DMEAS here below. Most algorithms are run over separate or all color channels. Most algorithms also contain a threshold value to zero out noise and / or amplify edges. Algorithm, Color, Threshold, or Window Control changes are accepted at the end of a valid measurement, the current measurement in progress is not affected. Software requests measurements in one of two ways:
q q
One shot - synchronous with respect to the microcontroller. Free Run - asynchronous with respect to the microcontroller.
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ADE3XXX
Data Measurement Block
In One-shot mode, the block indicates that measurement is valid through an auto-clear of start condition. In Free-running mode, the block indicates that measurement is valid through a polling bit. In Freerunning mode, a freeze bit is provided to freeze the results. Measurements continue with the polling bit active, but they are not updated if the Freeze bit is set.
2.12.1 Edge Intensity
The Edge Intensity measurement is the sum of the absolute value of the delta between adjacent pixels. A programmable threshold is applied to zero out noise and amplify edges. Equation: Delta_val = abs(pixelA - pixelB) - threshold; Delta_val = Delta_val < 0 ? 0: Delta_val; Sum += Delta_val; For all 3 color channels: Sum += Delta_val on Red channel + Delta_val on Green channel + Delta_val on Blue channel
2.12.2 Pixel Sum
The Pixel Sum is the sum of all selected pixels for either a specific color channel or all color channels within the window specified.
2.12.3 Min / Max
The Min / Max reports the minimum and maximum pixel found withing the window specified.
2.12.4 PCD
Pixel cumulative distribution function reports the total number of pixels greater than (or less than) a programmable threshold. To switch between pixels greater than or pixel less than the threshold, a control bit is provided in the DMM_Mode register when requesting a measurement.
2.12.5 H Position Min / Max
Horizontal position measures the start and end of video data in INCLKs relative to the posedge of hsync. Data horizontal start is defined as the number of INCLKs between posedge of hsync and the "first data pixel". First data pixel is either:
q q
first pixel greater than the programmable threshold value, or first pixel with the absolute value (current pixel - previous pixel) is greater than the programmable threshold value
Data horizontal end is defined as the number of INCLKs between posedge of hsync and the "last data pixel plus one". The search for the last pixels ends at the end of a window. Last data pixel plus one is either:
q q
pixel after the last pixel that is greater than the programmable threshold value,or last pixel with the absolute value(current pixel - previous pixel) is greater than the programmable threshold value.
When measurement is required, a control bit in the DMM_Mode register is used to switch between the two threshold methods for first and last pixels.
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Data Measurement Block
ADE3XXX
The first and last pixels are measured for each line, and the earliest first and latest last for the selected pixel area are reported out at the end of the measurement. The intention is that "last data pixel plus one" minus "first data pixel" is equal to the horizontal width of the video format.
2.12.6 V Position Min / Max
Vertical position measures the start and end of video data in hsyncs relative to the posedge of vsync. Data vertical start is defined as the number of hsyncs between posedge of vsync and the "first data pixel line". First data pixel line definition is the first line with at least one pixel greater then the programmable threshold. Data vertical end is defined as the number of hsyncs between posedge of vsync and the "first blanking line after data plus one". The first blanking line is detected and confirms that each subsequent line contains no data pixels. The confirmation of the first blanking line measurement ends at the posedge of vsync. First blanking line after data definition is the row after the last row with at least one pixel greater than the programmable threshold. The first and last data pixel lines are measured within a frame. The earliest first and latest last data pixels corresponding to the selected pixel area are reported out at the end of the measurement. The intention is that "data vertical end plus one" minus "data vertical start" is equal to the vertical height of the video format.
2.12.7 DE Size
DE Size measures the number of INCLKs per data enable. DVI input measures precisely the input image horizontal size. At the end of the measurement (DE falling edge), the measured value is compared to a programmed expected value +/- a programmed threshold. If the expected value is within the threshold, the DE_size_mismatch flag is not set. If the measued size is outside the threshold, the DE_size_mismatch flag is set. In Free-running mode, results are updated at every line. The DE_size_mismatch flag is set at DE falling edge and reset at DE rising edge. In One-shot mode, results are updated once and kept until they are cleared by software. The DE_size_mismatch flag can only be cleared when the reset flag bit is set by software.
Table 16: Data Measurement Registers (Sheet 1 of 5) Register Name
DMEAS_ALG_CTRL
Addr
0x0900
Mode
Bits
[7:5]
Default
Reserved 0x0 0x0 0x0
Description
R/W R/W R/W
[4] [3] [2:0]
Interlace Mode Enable 0: use data valid (TV mode only) 1: use data enable for data valid Algorithm 0x0: PHM Edge Intensity & Pixel Sum 0x1: DMM Min / Max 0x2: DMM PCD 0x3: DMM H position and V position 0x4: DMM DE size 0x5 - 0x7: Reserved
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ADE3XXX
Data Measurement Block
Table 16: Data Measurement Registers (Sheet 2 of 5)
Register Name
DMEAS_COLOR_CTRL
Addr
0x0901
Mode
Bits
[7:4]
Default
Reserved 0x0
Description
R/W
[3:2]
color channel for DMM Min / Max, PCD; does not apply to H position, V position 0x0: All 0x1: Red 0x2: Green 0x3: Blue
R/W
[1:0]
0x0
color channel for PHM Edge Intensity and Pixel Sum algorithms 0x0: All 0x1: Red 0x2: Green 0x3: Blue
DMEAS_THR_PHM_EDGE DMEAS_THR_DMM DMEAS_WIN_PHM_MINX_L DMEAS_WIN_PHM_MINX_H
0x0902 0x0903 0x0904 0x0905
R/W R/W R/W
[7:0] [7:0] [7:0] [7:4]
0x0 0x0 0x0
threshold value for PHM Edge Intensity algorithm threshold value for DMM Min / Max, PCD, H position, V position minimum X PHM window [7:0] Reserved minimum X PHM window [11:8] relative to hsync
R/W DMEAS_WIN_PHM_MAXX_L DMEAS_WIN_PHM_MAXX_H 0x0906 0x0907 R/W R/W
[3:0] [7:0] [7:4] [3:0] 0xFFF
maximum X PHM window [7:0] Reserved maximum X PHM window [11:8] Relative to hsync, must be less than input horizontal total (LLK_LINELEN for analog input).
DMEAS_WIN_PHM_MINY_L DMEAS_WIN_PHM_MINY_H
0x0908 0x0909
R/W
[7:0] [7:4]
0x0
minimum Y PHM window [7:0] Reserved minimum Y PHM window [11:8] relative to vsync
R/W DMEAS_WIN_PHM_MAXY_L DMEAS_WIN_PHM_MAXY_H 0x090A 0x090B R/W DMEAS_WIN_DMM_MINX_L DMEAS_WIN_DMM_MINX_H 0x090C 0x090D R/W R/W R/W
[3:0] [7:0] [7:4] [3:0] [7:0] [7:4] [3:0] 0x0 0x0 0xFFF
maximum Y PHM window [7:0] Reserved maximum Y PHM window [11:8] relative to vsync minimum X DMM window [7:0] Reserved minimum X DMM window [11:8] relative to hsync, does not apply for V position
DMEAS_WIN_DMM_MAXX_L DMEAS_WIN_DMM_MAXX_H
0x090E 0x090F
R/W
[7:0] [7:4]
0xFFF 0xFFF
maximum X DMM window [7:0] Reserved maximum X DMM window [11:8] relative to hsync, does not apply for V position
R/W
[3:0]
DMEAS_WIN_DMM_MINY_L
0x0910
R/W
[7:0]
0x0
minimum Y DMM window [7:0]
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Data Measurement Block
Table 16: Data Measurement Registers (Sheet 3 of 5) Register Name
DMEAS_WIN_DMM_MINY_H
ADE3XXX
Addr
0x0911
Mode
Bits
[7:4]
Default
Reserved
Description
R/W DMEAS_WIN_DMM_MAXY_L DMEAS_WIN_DMM_MAXY_H 0x0912 0x0913 R/W DMEAS_PHM_EDGESEL 0x0914 R/W R/W
[3:0] [7:0] [7:4] [3:0] [7:2] [1] 0xFFF 0x0 0xFFF
minimum Y DMM window [11:8] relative to vsync maximum Y DMM window [7:0] Reserved maximum Y DMM window [11:8] relative to vsync Reserved vsync edge select for PHM measurements 0: rising edge 1: falling edge
R/W
[0]
0x0
hsync edge select for PHM measurements 0: rising edge 1: falling edge
DMEAS_DMM_EDGESEL
0x0915 R/W
[7:2] [1] 0x0
Reserved vsync edge select for DMM measurements 0: rising edge 1: falling edge
R/W
[0]
0x0
hsync edge select for DMM measurements 0: rising edge 1: falling edge
DMEAS_PHM_MODE_CTRL
0x0916 R/W R/W
[7:5] [4] [3] 0x0 0x0
Reserved clear PHM result registers 0: Do not freeze the results in Free-running mode. New result will be available on the next and subsequent toggle of the polling bit. 1: Freeze the current results in Free-running mode. The polling bit will still toggle and the block continues to free run; however, results will not update. No meaning in one-shot mode.
R/W
[2]
0x0
PHM measurement polling bit. Toggles at the end of each measurement in free-run mode. Undefined in one-shot mode. PHM algorithm measurement start. In free-run mode it enables measurements. In one-shot mode it triggers the start of a measurement and is reset to zero when the measurement is complete. 0: PHM free-run mode. 1: PHM one-shot mode.
R/W
[1]
0x0
R/W
[0]
0x0
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ADE3XXX
Data Measurement Block
Table 16: Data Measurement Registers (Sheet 4 of 5)
Register Name
DMEAS_DMM_MODE_CTRL
Addr
0x0917
Mode
R/W
Bits
[7]
Default
0x0
Description
Listen to odd frame only. Applies only if the odd signal is present from YUV. The results in the Vertical Position algorithm are updated with only the odd frame if this bit is set. PCD algorithm 0: pixel < threshold 1: pixel >= threshold
R/W
[6]
0x0
R/W
[5]
0x0
horizontal position algorithm 0: pixel > threshold 1: abs (pixel - previous pixel) > threshold
R/W R/W
[4] [3]
0x0 0x0
clear DMM result registers 0: Do not freeze the results in Free-running mode. New result will be available on the next and subsequent toggle of the polling bit. 1: Freeze the current results in Free-running mode. The polling bit will still toggle and the block continues to free run; however, results will not update. No meaning in one-shot mode.
R/W
[2]
0x0
DMM measurement polling bit. Toggles at the end of each measurement in free-run mode. Undefined in one-shot mode. DMM algorithm measurement start. In free-run mode it enables measurements. In one-shot mode it triggers the start of a measurement and is reset to zero when the measurement is complete. 0: DMM Free-running mode. 1: DMM One-shot mode. DE Size expected result
R/W
[1]
0x0
R/W DMEAS_DMM_DE_REF_L DMEAS_DMM_DE_REF_H DMEAS_DMM_DE_TOL DMEAS_DMM_DE_RST 0x0918 0x0919 0x091A 0x091B R/W DMEAS_DATA_PHM_EDGE0 DMEAS_DATA_PHM_EDGE1 DMEAS_DATA_PHM_EDGE2 DMEAS_DATA_PHM_EDGE3 DMEAS_DATA_PHM_PSUM0 DMEAS_DATA_PHM_PSUM1 DMEAS_DATA_PHM_PSUM2 DMEAS_DATA_PHM_PSUM3 DMEAS_DATA_DMM_MIN DMEAS_DATA_DMM_MAX 0x091C 0x091D 0x091E 0x091F 0x0920 0x0921 0x0922 0x0923 0x0924 0x0925 R R R R R R R R R R R/W R/W R/W
[0] [7:0] [7:0] [7:0] [7:1] [0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0]
0x0 0x0
0x0
DE Size tolerance threshold value Reserved
0x0
Reset the DMM flag in One-shot mode Result of PHM edge intensity algorithm
Result for PHM pixel sum algorithm
Result for DMM Minimum pixel value found. Result for DMM Maxmum pixel value found.
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Programmable Nonlinearity Block
Table 16: Data Measurement Registers (Sheet 5 of 5) Register Name
DMEAS_DATA_DMM_PCD_L DMEAS_DATA_DMM_PCD_M DMEAS_DATA_DMM_PCD_H DMEAS_DATA_DMM_HPOSMIN_L DMEAS_DATA_DMM_HPOSMIN_H
ADE3XXX
Addr
0x0926 0x0927 0x0928 0x0929 0x092A
Mode
R R R R
Bits
[7:0] [7:0] [7:0] [7:0] [7:4]
Default
Description
Result for DMM pixel cumulative distribution
DMM Hposition of first pixel [7:0] Reserved DMM Hposition of first pixel [11:8] DMM Hposition of last pixel [7:0] Reserved DMM Hposition of last pixel [11:8] DMM Vposition of first line [7:0] Reserved DMM Vposition of first line [11:8] DMM Vposition of last line [7:0] Reserved DMM Vposition of last line [11:8] number of INCLKs per DE = input horizontal pixel size for DVI mode selection. Reserved DE measured value does not match expected value within the DE tolerance 0x0 Scratch Pad Registers
R DMEAS_DATA_DMM_HPOSMAX_L 0x092B R
[3:0] [7:0] [7:4]
DMEAS_DATA_DMM_HPOSMAX_H 0x092C R DMEAS_DATA_DMM_VPOSMIN_L DMEAS_DATA_DMM_VPOSMIN_H 0x092D 0x092E R DMEAS_DATA_DMM_VPOSMAX_L DMEAS_DATA_DMM_VPOSMAX_H 0x092F 0x0930 R DMEAS_DATA_DMM_SIZE_L DMEAS_DATA_DMM_SIZE_H DMEAS_DATA_DMM_DE_STATUS 0x0931 0x0932 0x0933 R DMEAS_SCR_PAD_0 DMEAS_SCR_PAD_1 DMEAS_SCR_PAD_2 DMEAS_SCR_PAD_3 DMEAS_SCR_PAD_4 DMEAS_SCR_PAD_5 DMEAS_SCR_PAD_6 DMEAS_SCR_PAD_7 DMEAS_SCR_PAD_8 DMEAS_SCR_PAD_9 DMEAS_SCR_PAD_10 DMEAS_SCR_PAD_11 DMEAS_SCR_PAD_12 DMEAS_SCR_PAD_13 DMEAS_SCR_PAD_14 DMEAS_SCR_PAD_15 0x0934 0x0935 0x0936 0x0937 0x0938 0x0939 0x093A 0x093B 0x093C 0x093D 0x093E 0x093F 0x0940 0x0941 0x0942 0x0943 R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R
[3:0] [7:0] [7:4] [3:0] [7:0] [7:4] [3:0] [7:0] [7:0] [7:1] [0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0]
2.13
Programmable Nonlinearity Block
The programmable nonlinearity (PNL) block performs a gamma type enhancement to all color channels prior to the scaler to suppress halo and roping effects. For best performance, tune the
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ADE3XXX
Scaler Block
PNL block to the LCD gamma value, then the post-scaler gamma RAM implements the corresponding inverse gamma function.
Table 17: PNL Registers Register Name
PNL_CTRL
Addr
0x0080
Mode
R/W
Bits
[7:6] [5:0]
Default
0x0 0x0 Reserved
Description
0x00: bypass 0x01 - 0x1F: gamma <1.0 0x20 - 0x3F: gamma >1.0 0x30: gamma = 2.2
2.14
Scaler Block
The scale module resizes images from one resolution to another. For this, a 3x3 non-separable scaling filter performs a dot product of the input pixel values with a weighting vector computed from the chosen filtering function. To sharpen text without introducing excessive artifacts, the output pixel contrast level is adjusted with the context value measured over a 3x3 grid in the relevant area of the source image. For proper scaler operation, set the SCLK frequency to be greater than the max of dclk and in_hpixel x dclk_freq / (dest_hpixel x pixel_avg).
Table 18: Scaler Block Registers (Sheet 1 of 3) Register Name Addr
0x0A00
Mode
R/W
Bits
[7:0]
Default
0x0
Description
input horizontal resolution in top 12 bits Bits [3:0] must be set to zero. If pixel averaging is necessary then this register contains the averaged, round-down resolution, e.g, if the original resolution is 65 and if the mode is averaging-by-2 then 32 should be programmed in this register.
SCL_SRC_HPIX_L
SCL_SRC_HPIX_H SCL_SRC_VPIX_L SCL_SRC_VPIX_H SCL_DES_HPIX_L SCL_DES_HPIX_H SCL_DES_VPIX_L SCL_DES_VPIX_H SCL_HPOS_L SCL_HPOS_H SCL_VPOS_E_L SCL_VPOS_E_H SCL_VPOS_O_L SCL_VPOS_O_H SCL_THRES_SLOPE
0x0A01 0x0A02 0x0A03 0x0A04 0x0A05 0x0A08 0x0A09 0x0A0A 0x0A0B 0x0A0E 0x0A0F 0x0A10 0x0A11 0x0A12
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
[7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:6] [5:0] 0x0 0x28 0x0 0x0 0x0 0x0 0x0 0x0 Input Vertical Resolution [3:0] must be set to 0. scaled active area width in pixels [15:4] = integer; [3:0] = fraction scaled active area height in lines [15:4] = integer; [3:0] = fraction horizontal position of upper left pixel of active output data [15:4] = integer; [3:0] = fraction vertical position of upper left pixel of output data for even/non-interlace frames [15:4] = integer; [3:0] = fraction vertical position of the upper left pixel of output data of odd fields bits [15:4] = integer; bits [3:0] = fraction Reserved slope of the contrast amplification function
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Scaler Block
Table 18: Scaler Block Registers (Sheet 2 of 3) Register Name
SCL_THRES_OFFSET_L SCL_THRES_OFFSET_H
ADE3XXX
Addr
0x0A13 0x0A14
Mode
R/W R/W R/W
Bits
[7:0] [7:2] [1:0] [7:2] [1] [0] [7:1]
Default
0x40 0x0 0x2 0x0 0x0 0x0
Description
offset of the contrast amplification function [7:0] Reserved offset of the contrast amplification function [9:8] Reserved 0: normal 1: TCON control of contrast amplification 0: contrast amplification enabled 1: bypass contrast amplification Reserved
SCL_CBBYPASS
0x0A15
R/W R/W R/W
SCL_CON_CAL_SEL
0x0A16 R/W
[0] [7:2]
0x0
0: context = max of RGB pk-pk 1: context = sum of RGB pk-pk 6b contrast amplification test data
SCL_TESTCON
0x0A17 R/W
[1:0]
0x0
0x0, 0x3: normal 0x1: force input data into the contrast amplifiation function to bits [7:2] 0x2: force the output context data to be bits [5:2]
SCL_LUT1 SCL_LUT2 SCL_LUT3 SCL_LUT4 SCL_LUT5 SCL_LUT6 SCL_LUT7 SCL_LUT8 SCL_LUT9 SCL_LUT10 SCL_LUT11 SCL_LUT12 SCL_LUT13 SCL_LUT14
0x0A18 0x0A19 0x0A1A 0x0A1B 0x0A1C 0x0A1D 0x0A1E 0x0A1F 0x0A20 0x0A21 0x0A22 0x0A23 0x0A24 0x0A25
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
[7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0]
0xFA 0xF7 0xF7 0xFC 0x2 0x0D 0x17 0x21 0x28 0x2C 0x2C 0x28 0x21 0x17
sigmoidal function LUT entry 1, 8b 2's complement sigmoidal function LUT entry 2, 8b 2's complement sigmoidal function LUT entry 3, 8b 2's complement sigmoidal function LUT entry 4, 8b 2's complement sigmoidal function LUT entry 5, 8b 2's complement sigmoidal function LUT entry 6, 8b 2's complement sigmoidal function LUT entry 7, 8b 2's complement sigmoidal function LUT entry 8, 8b 2's complement sigmoidal function LUT entry 9, 8b 2's complement sigmoidal function LUT entry 10, 8b 2's complement sigmoidal function LUT entry 11, 8b 2's complement sigmoidal function LUT entry 12, 8b 2's complement sigmoidal function LUT entry 13, 8b 2's complement sigmoidal function LUT entry 14, 8b 2's complement
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ADE3XXX
Table 18: Scaler Block Registers (Sheet 3 of 3) Register Name
SCL_LUT15 SCL_BGCOLOR_R SCL_BGCOLOR_G SCL_BGCOLOR_B SCL_BCOLOR_CTRL
Scaler Block
Addr
0x0A26 0x0A27 0x0A28 0x0A29 0x0A2A
Mode
R/W R/W R/W R/W R/W R/W
Bits
[7:0] [7:0] [7:0] [7:0] [7] [6]
Default
0x0C 0x0 0x0 0x0 0x0 0x0
Description
sigmoidal function LUT entry 15, 8b 2's complement red component of background color green component of background color blue component of background color 0: normal 1: force image to background color top & botton border control 0: pixel replicating 1: background color blending
R/W
[5]
0x0
left & right border control: 0: pixel replicating 1: background color blending
R/W R/W
[4] [3]
0x0 0x0
force output data as described in bit [1] when the maximum output vertical is reached. force output data as described in bit [1] when an abnormal codition is detected by the sync measurement module. When the scaler is not running, force the ouput data to black if this bit is 0 or to the background color if the bit is 1. If an abnormality is detected in the sync measurement module or if the maximum output vertical total has been reached, force the ouput data to black if this bit is 0 or to white if this bit is 1. During blanking, force output data to black if this bit is 0 or to the background color if this bit is 1. Reserved
R/W
[2]
0x0
R/W
[1]
0x0
R/W
[0]
0x0
SCL_AVERAGE_IK
0x0AF0 R/W
[7:3] [2:1] 0x0
0x0: bypass 0x1: horizontal average by 2 0x2: horizontal average by 4 0x3: horizontal average by 8 0: no pixel average 1: enable pixel averager This function is only necessary if the input horizontal resolution is greater than 1280 pixels.
R/W
[0]
0x0
SCL_FLIP_H_IK
0x0AF1 R/W
[7:1] [0] 0x0
Reserved horizontal flip enable
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Output Sequencer Block
ADE3XXX
2.15
Output Sequencer Block
The output sequencer module provides timing for the output video interface. It allows sufficient flexibility to support a broad range of Smart Panel applications as well. The timing unit is based on horizontal and vertical counters, which are locked with the input video stream.
Figure 4: Output Sequencer Block Diagram
Frame Synchronization
Due to the limited pixel memory of the chip, the output active video needs to be perfectly synchronized with the input active video. This mode of operation is called Frame Lock.
Figure 5: Frame Lock Operation
Timing Unit
The timing unit consists of a 12-bit horizontal and a 12-bit vertical counter, synchronized with the input video stream.
Signal Generation
The signal generation unit generates all fixed control signals like hsync, vsync and data enable as well as those required to run the internal data path. Also included, a generalized timing section supports flat panel TCON signals like polarity and other control signals.
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ADE3XXX
Output Sequencer Block
Table 19: Output Sequencer Registers (Sheet 1 of 2) Register Name
OSQ_CONTROL
Addr
0x0BC1
Mode
R R/W R/W R/W
Bits
[7] [6] [5] [4]
Default
Description
out_vmax detected, sticky bit
0x0 0x0 0x0
out_vmax detect reset interlace enable fractional line extend 0: +1 1: +2
R/W
[3]
0x0
frame lock reference 0: last input pixel 1: first input pixel
R/W
[2]
0x0
frame lock selection 0: last line variable 1: fixed line length
R R/W
[1] [0] 0x0
shutdown ready - current frame has completed, panel can now be shut down run sequencer when 1, otherwise stop at the end of the frame and set shutdown ready flag (bit [1]) the fraction of lines (/256) that are extended nominal output horizontal total [7:0] Reserved 0x0 0x0 nominal output horizontal total [11:8] minimum output vertical total, used to rearm for vert_enab trigger [7:0] Reserved 0x0 0x0 minimum output vertical total, used to rearm for vert_enab triggers [11:8] maximum output vertical total, prevents panel burn with loss of vert_enab trigger [7:0] Reserved 0x0 0x0 maximum output vertical total, prevents panel burn with loss of vert_enab triggers [11:8] delay of the vert_enab signal to the reset of the horizontal and vertical counters, even and noninterlaced modes [15:0]
OSQ_CLOCK_FRAC OSQ_OUT_HTOTAL_L OSQ_OUT_HTOTAL_H
0x0BC2 0x0BC3 0x0BC4
R/W R/W
[7:0] [7:0] [7:4]
0x0 0x0
R/W OSQ_OUT_VTOTAL_MIN_L OSQ_OUT_VTOTAL_MIN_H 0x0BC5 0x0BC6 R/W OSQ_VTOTAL_MAX_L OSQ_VTOTAL_MAX_H 0x0BC7 0x0BC8 R/W OSQ_VERTEN_DLY_E_L 0x0BC9 R/W R/W R/W
[3:0] [7:0] [7:4] [3:0] [7:0] [7:4] [3:0] [7:0]
OSQ_VERTEN_DLY_E_M OSQ_VERTEN_DLY_E_H
0x0BCA 0x0BCB
R/W
[7:0] [7:4]
0x0 Reserved 0x0 delay of the vert_enab signal to the reset of the horizontal and vertical counters, even and noninterlaced [19:16] delay of the vert_enab signal to the reset of the horizontal and vertical counters, odd frame in interlace mode only [15:0]
R/W
[3:0]
OSQ_VERTEN_DLY_O_L
0x0BCC
R/W
[7:0]
0x0
OSQ_VERTEN_DLY_O_M
0x0BCD
R/W
[7:0]
0x0
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Output Sequencer Block
Table 19: Output Sequencer Registers (Sheet 2 of 2) Register Name
OSQ_VERTEN_DLY_O_H
ADE3XXX
Addr
0x0BCE
Mode
Bits
[7:4]
Default
0x0 0x0 Reserved
Description
R/W
[3:0]
delay of the vert_enab signal to the reset of the horizontal and vertical counters, odd frame in interlace mode only [19:16] vertical count at which vsync goes high [7:0] Reserved vertical count at which vsync goes high [11:8] vertical count at which vsync goes low [7:0] Reserved vertical count at which vsync goes low [11:8] horizontal count at which hsync goes high [7:0] Reserved horizontal count at which hsync goes high [11:8] horizontal count at which hsync goes low [7:0] Reserved horizontal count at which hsync goes low [11:8] horizontal count at which enab goes high [7:0] Reserved horizontal count at which enab goes high [11:8] value must be greater than 0x01C
OSQ_VSYNC_SET_L OSQ_VSYNC_SET_H
0x0BCF 0x0BD0
R/W
[7:0] [7:4]
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
R/W OSQ_VSYNC_RST_L OSQ_VSYNC_RST_H 0x0BD1 0x0BD2 R/W OSQ_HSYNC_SET_L OSQ_HSYNC_SET_H 0x0BD3 0x0BD4 R/W OSQ_HSYNC_RST_L OSQ_HSYNC_RST_H 0x0BD5 0x0BD6 R/W OSQ_HENAB_SET_L OSQ_HENAB_SET_H 0x0BD7 0x0BD8 R/W R/W R/W R/W R/W
[3:0] [7:0] [7:4] [3:0] [7:0] [7:4] [3:0] [7:0] [7:4] [3:0] [7:0] [7:4] [3:0]
OSQ_HENAB_RST_L OSQ_HENAB_RST_H
0x0BD9 0x0BDA
R/W
[7:0] [7:4]
0x0
horizontal count at which enab goes low [7:0] Reserved horizontal count at which enab goes low [11:8]
R/W OSQ_VENAB_SET_L OSQ_VENAB_SET_H 0x0BDB 0x0BDC R/W OSQ_VENAB_RST_L OSQ_VENAB_RST_H 0x0BDD 0x0BDE R/W OSQ_OUT_VCOUNT 0x0BDF R R/W R/W
[3:0] [7:0] [7:4] [3:0] [7:0] [7:4] [3:0] [7:0] 0x0 0x0 0x0 0x0 0x0 0x0 0x0
vertical count at which enab goes high [7:0] Reserved vertical count at which enab goes high [11:8] vertical count at which enab goes low [7:0] Reserved vertical count at which enab goes low [11:8] vertical counter /16 indicating the current frame position
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ADE3XXX
Timing Controller (TCON) Block
2.16
Timing Controller (TCON) Block
The Output Timing Controller module provides timing for Smart Panel applications. The timing unit is based on horizontal and vertical counters locked with the output video stream. A set of programmable comparators provides all necessary time events to generate signals for the driver interface. Please refer to the programming tools for more details.
Figure 6: TCON Block Diagram
Table 20: TCON Registers (Sheet 1 of 6) Register Name
TCON_CONTROL
Addr.
0x0BC0
Mode
Bits
[7:3]
Default
Reserved 0 0 0 0
Description
R/W R/W R/W TCON_COMP_0_L TCON_COMP_0_H 0x0B10 0x0B11 R/W R/W R/W R/W TCON_COMP_1_L TCON_COMP_1_H TCON_COMP_2_L TCON_COMP_2_H TCON_COMP_3_L TCON_COMP_3_H TCON_COMP_4_L TCON_COMP_4_H TCON_COMP_5_L TCON_COMP_5_H TCON_COMP_6_L TCON_COMP_6_H 0x0B12 0x0B13 0x0B14 0x0B15 0x0B16 0x0B17 0x0B18 0x0B19 0x0B1A 0x0B1B 0x0B1C 0x0B1D R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
[2] [1] [0] [7:0] [7:5] [4] [3:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0]
0: no TCON pipe delay matching 1: TCON pipe delay enabled (normal) initialize SRTDs enableTCON count comparison value [7:0] Reserved 0: horizontal count compare 1: vertical count compare count comparison value [11:8]
0
refer to TCON_COMP_0 for definition
0
refer to TCON_COMP_0 for definition
0
refer to TCON_COMP_0 for definition
0
refer to TCON_COMP_0 for definition
0
refer to TCON_COMP_0 for definition
0
refer to TCON_COMP_0 for definition
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Timing Controller (TCON) Block
Table 20: TCON Registers (Sheet 2 of 6) Register Name
TCON_COMP_7_L TCON_COMP_7_H TCON_COMP_8_L TCON_COMP_8_H TCON_COMP_9_L TCON_COMP_9_H TCON_COMP_10_L TCON_COMP_10_H TCON_COMP_11_L TCON_COMP_11_H TCON_COMP_12_L TCON_COMP_12_H TCON_COMP_13_L TCON_COMP_13_H TCON_COMP_14_L TCON_COMP_14_H TCON_COMP_15_L TCON_COMP_15_H TCON_COMP_16_L TCON_COMP_16_H TCON_COMP_17_L TCON_COMP_17_H TCON_COMP_18_L TCON_COMP_18_H TCON_COMP_19_L TCON_COMP_19_H TCON_COMP_20_L TCON_COMP_20_H TCON_COMP_21_L TCON_COMP_21_H TCON_COMP_22_L TCON_COMP_22_H TCON_COMP_23_L TCON_COMP_23_H TCON_COMP_24_L TCON_COMP_24_H TCON_COMP_25_L TCON_COMP_25_H
ADE3XXX
Addr.
0x0B1E 0x0B1F 0x0B20 0x0B21 0x0B22 0x0B23 0x0B24 0x0B25 0x0B26 0x0B27 0x0B28 0x0B29 0x0B2A 0x0B2B 0x0B2C 0x0B2D v0B2E v0B2F 0x0B30 0x0B31 0x0B32 0x0B33 0x0B34 0x0B35 0x0B36 0x0B37 0x0B38 0x0B39 0x0B3A 0x0B3B 0x0B3C 0x0B3D 0x0B3E 0x0B3F 0x0B40 0x0B41 0x0B42 0x0B43
Mode
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bits
[7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0]
Default
0
Description
refer to TCON_COMP_0 for definition
0
refer to TCON_COMP_0 for definition
0
refer to TCON_COMP_0 for definition
0
refer to TCON_COMP_0 for definition
0
refer to TCON_COMP_0 for definition
0
refer to TCON_COMP_0 for definition
0
refer to TCON_COMP_0 for definition
0
refer to TCON_COMP_0 for definition
0
refer to TCON_COMP_0 for definition
0
refer to TCON_COMP_0 for definition
0x0
refer to TCON_COMP_0 for definition
0x0
refer to TCON_COMP_0 for definition
0x0
refer to TCON_COMP_0 for definition
0x0
refer to TCON_COMP_0 for definition
0x0
refer to TCON_COMP_0 for definition
0x0
refer to TCON_COMP_0 for definition
0x0
refer to TCON_COMP_0 for definition
0x0
refer to TCON_COMP_0 for definition
0x0
refer to TCON_COMP_0 for definition
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ADE3XXX
Timing Controller (TCON) Block
Table 20: TCON Registers (Sheet 3 of 6)
Register Name
TCON_COMP_26_L TCON_COMP_26_H TCON_COMP_27_L TCON_COMP_27_H TCON_SRTD_0
Addr.
0x0B44 0x0B45 0x0B46 0x0B47 0x0B50
Mode
R/W R/W R/W R/W
Bits
[7:0] [7:0] [7:0] [7:0] [7:4]
Default
0x0
Description
refer to TCON_COMP_0 for definition
0x0
refer to TCON_COMP_0 for definition
Reserved 0x0 0x0 SRTD initialization state 0x0: f (A&B,&C&D,0,0) 0x1: f (A&B,&C&D,0,0) 0x2: f (A&B,&C&D,0,0) 0x3: f (0,0,A&B,0) 0x4: f (0,0,0,A&B) 0x5: f (0,0,0,A|B) 0x6: f (0,0,0,A^B) 0x7: f (0,0,0,!(A&B)) where f(Set, Reset, Toggle, Dflop) is a configurable logic/flop element
R/W R/W
[3] [2:0]
TCON_SRTD_1 TCON_SRTD_2 TCON_SRTD_3 TCON_SRTD_4 TCON_SRTD_5 TCON_SRTD_6 TCON_SRTD_7 TCON_SRTD_8 TCON_SRTD_9 TCON_SRTD_10 TCON_SRTD_11 TCON_SRTD_12 TCON_SRTD_13 TCON_SRTD_14 TCON_SRTD_15 TCON_SRTD_16 TCON_SRTD_17 TCON_SRTD_18 TCON_SRTD_19 TCON_SRTD_20 TCON_SRTD_21 TCON_SRTD_22 TCON_SRTD_23 TCON_SRTD_24 TCON_SRTD_25 TCON_SRTD_26
0x0B51 0x0B52 0x0B53 0x0B54 0x0B55 0x0B56 0x0B57 0x0B58 0x0B59 0x0B5A 0x0B5B 0x0B5C 0x0B5D 0x0B5E 0x0B5F 0x0B60 0x0B61 0x0B62 0x0B63 0x0B64 0x0B65 0x0B66 0x0B67 0x0B68 0x0B69 0x0B6A
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
[7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0]
refer to TCON_srtd_0 for definition refer to TCON_srtd_0 for definition refer to TCON_srtd_0 for definition refer to TCON_srtd_0 for definition refer to TCON_srtd_0 for definition refer to TCON_srtd_0 for definition refer to TCON_srtd_0 for definition refer to TCON_srtd_0 for definition refer to TCON_srtd_0 for definition refer to TCON_srtd_0 for definition refer to TCON_srtd_0 for definition refer to TCON_srtd_0 for definition refer to TCON_srtd_0 for definition refer to TCON_srtd_0 for definition refer to TCON_srtd_0 for definition refer to TCON_srtd_0 for definition refer to TCON_srtd_0 for definition refer to TCON_srtd_0 for definition refer to TCON_srtd_0 for definition refer to TCON_srtd_0 for definition refer to TCON_srtd_0 for definition refer to TCON_srtd_0 for definition refer to TCON_srtd_0 for definition refer to TCON_srtd_0 for definition refer to TCON_srtd_0 for definition refer to TCON_srtd_0 for definition
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Timing Controller (TCON) Block
Table 20: TCON Registers (Sheet 4 of 6) Register Name
TCON_SRTD_27 TCON_SRTD_28 TCON_SRTD_29 TCON_SRTD_30 TCON_SRTD_31 TCON_X_0
ADE3XXX
Addr.
0x0B6B 0x0B6C 0x0B6D 0x0B6E 0x0B6F 0x0B80
Mode
R/W R/W R/W R/W R/W
Bits
[7:0] [7:0] [7:0] [7:0] [7:0] [7:6]
Default
Description
refer to TCON_srtd_0 for definition refer to TCON_srtd_0 for definition refer to TCON_srtd_0 for definition refer to TCON_srtd_0 for definition refer to TCON_srtd_0 for definition Reserved
R/W
[5:0]
0x0
Input Selection for SRTD_0.A 0x00: 0 0x01: 1 0x02: external TCON input pin 0x03: I2C SRTD init bit 0x04 - 0x1F: comp0 - comp27 0x20 - 0x37: SRTD8 - SRTD31 0x38: 2 frame + 1 line + 2 pixel toggle 0x39: 2 frame + 2 line + 1 pixel toggle 0x3A: HCOUNT[0] 0x3B: HCOUNT[1] 0x3C: HCOUNT[0] 0x3D: HCOUNT[1] 0x3E: FCOUNT[0] 0x3F: FCOUNT[1]
TCON_X_1 TCON_X_2 TCON_X_3 TCON_X_4 TCON_X_5 TCON_X_6 TCON_X_7 TCON_X_8 TCON_X_9 TCON_X_10 TCON_X_11 TCON_X_12 TCON_X_13 TCON_X_14 TCON_X_15 TCON_X_16 TCON_X_17 TCON_X_18 TCON_X_19 TCON_X_20
0x0B81 0x0B82 0x0B83 0x0B84 0x0B85 0x0B86 0x0B87 0x0B88 0x0B89 0x0B8A 0x0B8B 0x0B8C 0x0B8D 0x0B8E 0x0B8F 0x0B90 0x0B91 0x0B92 0x0B93 0x0B94
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
[7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0]
Input Selection for SRTD_0.B1 Input Selection for SRTD_1.A1 Input Selection for SRTD_1.B1 Input Selection for SRTD_2.A1 Input Selection for SRTD_2.B1 Input Selection for SRTD_3.A1 Input Selection for SRTD_3.B1 Input Selection for SRTD_4.A1 Input Selection for SRTD_4.B1 Input Selection for SRTD_5.A1 Input Selection for SRTD_5.B1 Input Selection for SRTD_6.A1 Input Selection for SRTD_6.B1 Input Selection for SRTD_7.1 Input Selection for SRTD_7.B1 Input Selection for SRTD_8.1 Input Selection for SRTD_8.B1 Input Selection for SRTD_9.A1 Input Selection for SRTD_9.B1 Input Selection for SRTD_10.A1
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ADE3XXX
Timing Controller (TCON) Block
Table 20: TCON Registers (Sheet 5 of 6)
Register Name
TCON_X_21 TCON_X_22 TCON_X_23 TCON_X_24 TCON_X_25 TCON_X_26 TCON_X_27 TCON_X_28 TCON_X_29 TCON_X_30 TCON_X_31 TCON_X_32 TCON_X_33 TCON_X_34 TCON_X_35 TCON_X_36 TCON_X_37 TCON_X_38 TCON_X_39 TCON_X_40 TCON_X_41 TCON_X_42 TCON_X_43 TCON_X_44 TCON_X_45 TCON_X_46 TCON_X_47 TCON_X_48 TCON_X_49 TCON_X_50 TCON_X_51 TCON_X_52 TCON_X_53 TCON_X_54
Addr.
0x0B95 0x0B96 0x0B97 0x0B98 0x0B99 0x0B9A 0x0B9B 0x0B9C 0x0B9D 0x0B9E 0x0B9F 0x0BA0 0x0BA1 0x0BA2 0x0BA3 0x0BA4 0x0BA5 0x0BA6 0x0BA7 0x0BA8 0x0BA9 0x0BAA 0x0BAB 0x0BAC 0x0BAD 0x0BAE 0x0BAF 0x0BB0 0x0BB1 0x0BB2 0x0BB3 0x0BB4 0x0BB5 0x0BB6
Mode
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bits
[7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0]
Default
Description
Input Selection for SRTD_10.B1 Input Selection for SRTD_11.A1 Input Selection for SRTD_11.B1 Input Selection for SRTD_12.A1 Input Selection for SRTD_12.B1 Input Selection for SRTD_13.A1 Input Selection for SRTD_13.B1 Input Selection for SRTD_14.A1 Input Selection for SRTD_14.B1 Input Selection for SRTD_15.A1 Input Selection for SRTD_15.B1 Input Selection for SRTD_16.A1 Input Selection for SRTD_16.B1 Input Selection for SRTD_17.A1 Input Selection for SRTD_17.B1 Input Selection for SRTD_18.A1 Input Selection for SRTD_18.B1 Input Selection for SRTD_19.A1 Input Selection for SRTD_19.B1 Input Selection for SRTD_20.A1 Input Selection for SRTD_20.B1 Input Selection for SRTD_21.A1 Input Selection for SRTD_21.B1 Input Selection for SRTD_22.A1 Input Selection for SRTD_22.B1 Input Selection for SRTD_23.A1 Input Selection for SRTD_23.B1 Input Selection for SRTD_24.A1 Input Selection for SRTD_24.B1 Input Selection for SRTD_25.A1 Input Selection for SRTD_25.B1 Input Selection for SRTD_26.A1 Input Selection for SRTD_26.B1 Input Selection for SRTD_27.A1
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Pattern Generator Block
Table 20: TCON Registers (Sheet 6 of 6) Register Name
TCON_X_55 TCON_X_56 TCON_X_57 TCON_X_58 TCON_X_59 TCON_X_60 TCON_X_61 TCON_X_62 TCON_X_63
ADE3XXX
Addr.
0x0BB7 0x0BB8 0x0BB9 0x0BBA 0x0BBB 0x0BBC 0x0BBD 0x0BBE 0x0BBF
Mode
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bits
[7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0]
Default
Description
Input Selection for SRTD_27.B1 Input Selection for SRTD_28.A1 Input Selection for SRTD_28.B1 Input Selection for SRTD_29.A1 Input Selection for SRTD_29.B1 Input Selection for SRTD_30.A1 Input Selection for SRTD_30.B1 Input Selection for SRTD_31.A1 Input Selection for SRTD_31.B1
1. Refer to register TCON_X_O for definition.
2.17
Pattern Generator Block
The integrated Pattern Generator displays a set of graphic patterns to help debugging systems and test LCD panels. It is located ahead of the color management block, all generated colors are subject to further transforms. The screen can be split into a programmable grid of up to 8x8 areas. One of two independent programmable patterns are displayed in each area.
Screen Split
A set of eight Grid registers grid0 - grid7, each with 8 bits, represents a block map of the grid (8x8 blocks). Each bit from the Grid registers represents one rectangular (gridX)x(gridY) block of pixels which covers the LCD screen display area. Within these registers, a 0 selects Pattern 0 (defined below) and a 1 selects Pattern 1.
Figure 7: Pattern Generator: Screen Split
All cells are the same size, defined by one horizontal and one vertical grid block size registers gridX and gridY.
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ADE3XXX
Pattern Generator Block
When the programmed block size corresponds to a larger 8x8 grid than the total screen area, only the blocks or part of blocks included in the output screen space are rendered. The 8x8 block set is upper left justified. All blocks from the right and bottom sides which are outside the total display area are not rendered. When the programmed block size corresponds to a smaller 8x8 grid than the total screen area, the part of the screen area which is outside the 8x8 grid is forced to black.
Pattern Engine
The pattern generator has two pattern display engines to display two patterns simultaneously on the LCD screen. Each engine displays horizontal or vertical bicolor stripes, bicolor checkers, color bars, gray scales or color scales. It is also possible to select the video stream from the scaler as a pattern. The pattern engine displays a bi-directional x-y symmetric pattern. Two 24b colors, C0 and C1, are alternately displayed with a horizontal period of Width and vertical period of Height. Programming a large Width and a small Height generates horizontal bars whereas the opposite generates vertical bars. Programming small numbers for Width and Height generates checker patterns. Both patterns are also given X and Y offset attributes, they can be centered inside the grid blocks. A gradient effect can be applied independently on each pattern, to either or both horizontal and vertical directions. The gradient effect takes two parameters: STEP and DELTA that define a ramp.
Borders
The border generator adds a single pixel width border to the whole display area. Each side color of the display is selectable among 8 independent colors.
Table 21: PGEN Registers (Sheet 1 of 4) Register Name
PGEN_PGEN_ENAB
Addr
0x0600
Mode
R/W
Bits
[7:1] [0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:4] [3:0] [7:0] [7:4] [3:0] [7:0] [7:4] [3:0] [7:4] [3:0]
Default
Reserved 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
Description
0 = disable PGEN block 1 = enable PGEN block Grid Row 0 Grid Row 1 Grid Row 2 Grid Row 3 Grid Row 4 Grid Row 5 Grid Row 6 Grid Row 7 width of a grid block in pixels [7:0] Reserved width of a grid block in pixels [11:8] height of a grid block in pixels [7:0] Reserved height of a grid block in pixels [11:8] grid block horizontal offset in pixels [7:0] Reserved grid block horizontal offset in pixels [11:8] grid block vertical offset in pixels
PGEN_GRID0 PGEN_GRID1 PGEN_GRID2 PGEN_GRID3 PGEN_GRID4 PGEN_GRID5 PGEN_GRID6 PGEN_GRID7 PGEN_GRID_X_L PGEN_GRID_X_H PGEN_GRID_Y_L PGEN_GRID_Y_H PGEN_GRID_X_OFFSET_X_L PGEN_GRID_X_OFFSET_X_H PGEN_GRID_Y_OFFSET_Y_L PGEN_GRID_Y_OFFSET_Y_H
0x0601 0x0602 0x0603 0x0604 0x0605 0x0606 0x0607 0x0608 0x0609 0x060A
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
0x060B 0x060C
R/W R/W
0x060D 0x060E
R/W R/W
0x060F 0x0610
R/W R/W
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Pattern Generator Block
Table 21: PGEN Registers (Sheet 2 of 4) Register Name
PGEN_P0_MODE
ADE3XXX
Addr
0x0611
Mode
R/W R/W R/W R/W
Bits
[7:5] [4:2] [1]
Default
0x0 0x0 0x0
Description
pattern 0 control number of bars in C0 number of bars in C1 0: pattern continues to progress across block boundaries 1: block boundaries cause the pattern to restart 0: normal mode 1: C0 = video bypass pattern 1 control number of bars in C0 number of bars in C1 0: pattern continues to progress across block boundaries 1: block boundaries cause the pattern to restart 0: normal mode 1: C0 = video bypass Pattern 0 Bar Width [7:0] Reserved Pattern 0 Bar Width [11:8] Pattern 0 Horizontal Offset [7:0] Reserved Pattern 0 Horizontal Offset [11:8] Pattern 0 Bar Height [7:0] Pattern 0 Vertical Sequence Increment Pattern 0 Bar Height [11:8] Pattern 0 Vertical Offset [7:0] Reserved Pattern 0 Vertical Offset [11:8] Pattern 1 Bar Width [7:0] Reserved Pattern 1 Bar Width [11:8] Pattern 1 Horizontal Offset [7:0] Reserved Pattern 1 Horizontal Offset [11:8] Pattern 1 Bar Height [7:0] Pattern 1 Vertical Sequence Increment Pattern 1 Bar Height [11:8] Pattern 1 Vertical Offset [7:0] Reserved Pattern 1 Vertical Offset [11:8] Pattern 0 Color C0 - Red Pattern 0 Color C0 - Green Pattern 0 Color C0 - Blue Pattern 0 Color C1 - Red Pattern 0 Color C1 - Green
R/W PGEN_P1_MODE 0x0612 R/W R/W R/W
[0]
0x0
[7:5] [4:2] [1]
0x0 0x0 0x0
R/W PGEN_P0_WIDTH_X_L PGEN_P0_WIDTH_X_H PGEN_P0_WIDTH_X_OFFSET_L PGEN_P0_WIDTH_X_OFFSET_H PGEN_P0_HEIGHT_Y_L PGEN_P0_HEIGHT_Y_H PGEN_P0_HEIGHT_Y_OFFSET_L PGEN_P0_HEIGHT_Y_OFFSET_H PGEN_P1_WIDTH_X_L PGEN_P1_WIDTH_X_H PGEN_P1_WIDTH_X_OFFSET_L PGEN_P1_WIDTH_X_OFFSET_H PGEN_P1_HEIGHT_Y_L PGEN_P1_HEIGHT_Y_H PGEN_P1_HEIGHT_Y_OFFSET_L PGEN_P1_HEIGHT_Y_OFFSET_H PGEN_P0_COLOR_R_C0 PGEN_P0_COLOR_G_C0 PGEN_P0_COLOR_B_C0 PGEN_P0_COLOR_R_C1 PGEN_P0_COLOR_G_C1 0x0613 0x0614 R/W 0x0615 0x0616 R/W 0x0617 0x0618 0x0619 0x061A R/W 0x061B 0x061C R/W 0x061D 0x061E R/W 0x061F 0x0620 0x0621 0x0622 R/W 0x0623 0x0624 0x0625 0x0626 0x0627 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
[0] [7:0] [7:4] [3:0] [7:0] [7:4] [3:0] [7:0] [7:4] [3:0] [7:0] [7:4] [3:0] [7:0] [7:4] [3:0] [7:0] [7:4] [3:0] [7:0] [7:4] [3:0] [7:0] [7:4] [3:0] [7:0] [7:0] [7:0] [7:0] [7:0]
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
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ADE3XXX
Table 21: PGEN Registers (Sheet 3 of 4) Register Name
PGEN_P0_COLOR_B_C1 PGEN_P1_COLOR_R_C0 PGEN_P1_COLOR_G_C0 PGEN_P1_COLOR_B_C0 PGEN_P1_COLOR_R_C1 PGEN_P1_COLOR_G_C1 PGEN_P1_COLOR_B_C1 PGEN_P0_GRADDELTA_R PGEN_P0_GRADDELTA_G PGEN_P0_GRADDELTA_B PGEN_P0_GRADSTEP_X PGEN_P0_GRADSTEP_Y PGEN_P1_GRADDELTA_R PGEN_P1_GRADDELTA_G PGEN_P1_GRADDELTA_B PGEN_P1_GRADSTEP_X PGEN_P1_GRADSTEP_Y PGEN_P0_SEQ_COL0_COL1
Pattern Generator Block
Addr
0x0628 0x0629 0x062A 0x062B 0x062C 0x062D 0x062E 0x062F 0x0630 0x0631 0x0632 0x0633 0x0634 0x0635 0x0636 0x0637 0x0638 0x0639
Mode
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bits
[7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7] [6:4] [3] [2:0] [7] [6:4] [3] [2:0] [7] [6:4] [3] [2:0] [7] [6:4] [3] [2:0] [7] [6:4] [3] [2:0] [7] [6:4] [3] [2:0] [7] [6:4] [3] [2:0]
Default
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
Description
Pattern 0 Color C1 - Blue Pattern 1 Color C0 - Red Pattern 1 Color C0 - Green Pattern 1 Color C0 - Blue Pattern 1 Color C1 - Red Pattern 1 Color C1 - Green Pattern 1 Color C1 - Blue Pattern 0 Gradient Delta on Red Pattern 0 Gradient Delta on Green Pattern 0 Gradient Delta on Blue Pattern 0 Gradient Horizontal Step Pattern 0 Gradient Vertical Step Pattern 1 Gradient Delta on Red Pattern 1 Gradient Delta on Green Pattern 1 Gradient Delta on Blue Pattern 1 Gradient Horizontal Step Pattern 1 Gradient Vertical Step Reserved Pattern 0 Bar 1 Color Reserved Pattern 0 Ba R0 Color Reserved Pattern 0 Bar 3 Color Reserved Pattern 0 Bar 2 Color Reserved Pattern 0 Bar 5 Color Reserved Pattern 0 Bar 4 Color Reserved Pattern 0 Bar 7 Color Reserved Pattern 0 Bar 6 Color Reserved Pattern 1 Bar 1 Color Reserved Pattern 1 Bar 0 Color Reserved Pattern 1 Bar 3 Color Reserved Pattern 1 Bar 2 Color Reserved Pattern 1 Bar 5 Color Reserved Pattern 1 Bar 4 Color
PGEN_P0_SEQ_COL2_COL3
0x063A R/W R/W
PGEN_P0_SEQ_COL4_COL5
0x063B R/W R/W
PGEN_P0_SEQ_COL6_COL7
0x063C R/W R/W
PGEN_P1_SEQ_COL0_COL1
0x063D R/W R/W
PGEN_P1_SEQ_COL2_COL3
0x063E R/W R/W
PGEN_P1_SEQ_COL4_COL5
0x063F R/W R/W
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SRGB Block
Table 21: PGEN Registers (Sheet 4 of 4) Register Name
PGEN_P1_SEQ_COL6_COL7
ADE3XXX
Addr
0x0640
Mode
R/W R/W
Bits
[7] [6:4] [3] [2:0] [7] [6] [5] [4] [3] [2] [1] [0] [7] [6] [5] [4] [3] [2] [1] [0] [7:0] [7:4] [3:0] [7:0] [7:4] [3:0]
Default
Reserved 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
Description
Pattern 1 Bar 7 Color Reserved Pattern 1 Bar 6 Color Top Border Enable Top Border Red; 0 = Off, 1= On Top Border Green; 0 = Off, 1= On Top Border Blue; 0 = Off, 1= On Bottom Border Enable Bottom Border Red; 0 = Off, 1= On Bottom Border Green; 0 = Off, 1= On Bottom Border Blue; 0 = Off, 1= On Left Border Enable Left Border Red; 0 = Off, 1= On Left Border Green; 0 = Off, 1= On Left Border Blue; 0 = Off, 1= On Right Border Enable Right Border Red; 0 = Off, 1= On Right Border Green; 0 = Off, 1= On Right Border Blue; 0 = Off, 1= On Total Horizontal Size [7:0] Reserved Total Horizontal Size [11:8] Total Vertical Size [7:0] Reserved Total Vertical Size [11:8]
PGEN_B_TOP_BOTTOM
0x0641
R/W R/W R/W R/W R/W R/W R/W R/W
PGEN_B_LEFT_RIGHT
0x0642
R/W R/W R/W R/W R/W R/W R/W R/W
PGEN_X_TOTAL_L PGEN_X_TOTAL_H PGEN_Y_TOTAL_L PGEN_Y_TOTAL_H
0x0643 0x0644
R/W R/W
0x0645 0x0646
R/W R/W
2.18
SRGB Block
The sRGB block performs two primary functions: 1. Parametric gamma correction on multiple windows or full screen for video enhancement in a window and digital contrast/brightness control. The window coordinates are set by TCON registers. 2. 3D color cube warping RGB color space.
2.18.1 Parametric Gamma Correction and Digital Contrast/Brightness Control
The function is applied to the entire window by programming the window control to full screen. Each color channel acts independently. Simple digital contrast and brightness are programmable with this hardware function. The desired window coordinates are programmed into the TCON.
2.18.2 Color Space Warp
The 8 corners of the color cube are independently controlled in 3D space with smooth interpolation of intermediate colors. Registers are 2's complement color delta's. For example, to make WHITE more like RED, program SRGB_WHITE_R to a small positive value.
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ADE3XXX
SRGB Block
Figure 8: Color Space Warp
Color Space Warp
IN
OUT
Table 22: SRGB Registers (Sheet 1 of 2) Register Name
SRGB_CTRL
Addr
0x0D00
Mode
R/W R/W
Bits
[7:6] [5:4]
Default
0x0 0x0 Reserved
Description
GAMMA_B Control 0x0: Disable 0x1: Full Screen 0x2: Windowed 0x3: Reserved
R/W
[3:2]
0x0
GAMMA_A Control 0x0: Disable 0x1: Full Screen 0x2: Windowed 0x3: Reserved
R/W
[1:0]
0x0
SRGB Control 0x0: Disabled 0x1: Full Screen 0x2: Windowed 0x3: Reserved
SRGB_BLACK_R SRGB_BLACK_G SRGB_BLACK_B SRGB_RED_R SRGB_RED_G SRGB_RED_B SRGB_GREEN_R SRGB_GREEN_G SRGB_GREEN_B SRGB_BLUE_R SRGB_BLUE_G SRGB_BLUE_B SRGB_YELLOW_R SRGB_YELLOW_G SRGB_YELLOW_B SRGB_CYAN_R
0x0D01 0x0D02 0x0D03 0x0D04 0x0D05 0x0D06 0x0D07 0x0D08 0x0D09 0x0D0A 0x0D0B 0x0D0C 0x0D0D 0x0D0E 0x0D0F 0x0D10
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
[7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0]
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
Black Point Red Delta Black Point Green Delta Black Point Blue Delta Red Point Red Delta Red Point Green Delta Red Point Blue Delta Green Point Red Delta Green Point Green Delta Green Point Blue Delta Blue Point Red Delta Blue Point Green Delta Blue Point Blue Delta Yellow Point Red Delta Yellow Point Green Delta Yellow Point Blue Delta Cyan Point Red Delta
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OSD Block
Table 22: SRGB Registers (Sheet 2 of 2) Register Name
SRGB_CYAN_G SRGB_CYAN_B SRGB_MAGENTA_R SRGB_MAGENTA_G SRGB_MAGENTA_B SRGB_WHITE_R SRGB_WHITE_G SRGB_WHITE_B SRGB_GAMMA_A_RED_A SRGB_GAMMA_A_RED_B SRGB_GAMMA_A_RED_C SRGB_GAMMA_A_GREEN_A SRGB_GAMMA_A_GREEN_B SRGB_GAMMA_A_GREEN_C SRGB_GAMMA_A_BLUE_A SRGB_GAMMA_A_BLUE_B SRGB_GAMMA_A_BLUE_C SRGB_GAMMA_B_RED_A SRGB_GAMMA_B_RED_B SRGB_GAMMA_B_RED_C SRGB_GAMMA_B_GREEN_A SRGB_GAMMA_B_GREEN_B SRGB_GAMMA_B_GREEN_C SRGB_GAMMA_B_BLUE_A SRGB_GAMMA_B_BLUE_B SRGB_GAMMA_B_BLUE_C
ADE3XXX
Addr
0x0D11 0x0D12 0x0D13 0x0D14 0x0D15 0x0D16 0x0D17 0x0D18 0x0D19 0x0D1A 0x0D1B 0x0D1C 0x0D1D 0x0D1E 0x0D1F 0x0D20 0x0D21 0x0D22 0x0D23 0x0D24 0x0D25 0x0D26 0x0D27 0x0D28 0x0D29 0x0D2A
Mode
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bits
[7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0]
Default
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
Description
Cyan Point Green Delta Cyan Point Blue Delta Magenta Point Red Delta Magenta Point Green Delta Magenta Point Blue Delta White Point Red Delta White Point Green Delta White Point Blue Delta Parametric A Gamma A Red, Gamma Parametric A Gamma B Red, Contrast Parametric A Gamma C Red, Brightness Parametric A Gamma A Green, Gamma Parametric A Gamma B Green, Contrast Parametric A Gamma C Green, Brightness Parametric A Gamma A Blue, Gamma Parametric A Gamma B Blue, Contrast Parametric A Gamma C Blue, Brightness Parametric B Gamma A Red, Gamma Parametric Gamma B Red, Contrast Parametric Gamma C Red, Brightness Parametric Gamma A Green, Gamma Parametric Gamma B Green, Contrast Parametric Gamma C Green, Brightness Parametric Gamma A Blue, Gamma Parametric Gamma B Blue, Contrast Parametric Gamma C Blue, Brightness
2.19
OSD Block
Introduction The integrated on-screen display (OSD) controller is a character-based overlay with a high level of features and over 100Kbyte of on-board dedicated RAM storage. Features
q q q q q q q
15 row by 30 column character-mapped display Four user-definable windows 12x18-pixel characters with optional horizontal and vertical doubling on a row-by-row basis Two 16-entry 24-bit RGB user-definable color maps 192 RAM-based monochrome 1bpp characters 64 RAM-based graphics 4bpp characters Text character attributes: foreground/background color, blinking
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ADE3XXX
q q q q
OSD Block
Graphics character attributes: per-pixel color, vertical/horizontal mirroring Row attributes: double width, double height Window attributes: window visibility, position, size, border shadow, color table Global attributes: OSD visibility, OSD screen position, alpha fade in/fade out, global size doubling, rotation in ninety-degree increments Single-bit enable/disable
q
For information on OSD programming, see the OSD Programming Manual. OSD Access via I2C The OSD uses a dedicated memory space accessible through an I2C port. The data stream sent to the OSD register starts with two header bytes. These specify the type of transfer and the row/ column position for screen map transfers, the character index for font definition transfers, or the color index for color map transfers. A stream of OSD writes to the OSD I2C register can fill in a segment of the OSD memory space with an internal auto-incrementing index register. The protocol is as follows: 1. Issue a start sequence with the R/W bit set to W. 2. Write to the OSD register. The first byte transferred is the index of the first internal OSD register to be written. The next byte contains the data to be written to that register. Subsequent bytes are written to successive internal OSD registers. 3. Continue writing data bytes until the desired range of OSD internal registers has been written (the ADE3XXX device will issue an ACK on each transfer). 4. Issue an I2C stop sequence. Character Display There are two 96-character monochrome fonts and two 32-character four-bit color fonts, a total of 256 characters. The four bits of color are an index into one of two 16 entry color look-up tables. Entries in the color look-up table specify a 24-bit RGB color. All fonts and the color look-up table are RAM-based and must be downloaded to the OSD's internal RAM before use. Font addressing is as follows: character indexes 0x00-0x1F refer to color font 0, 0x20-0x7F refer to monochrome font 0, 0x80-0x9F refer to color font 1 and 0xA0-0xFF refer to monochrome font 1. Screen Map The OSD uses a character map of 15 rows x 30 columns. Each character occupies one byte. The value of each byte indicates the character to display. The OSD character map is addressed by specifying the row and column as part of the data transfer. Attribute Map The attribute map is defined as 16 rows by 31 columns. It has an extra row and an extra column compared to the screen map. The values corresponding to printable row/column addresses provide character attributes. Each character on the screen has an attribute byte specifying (in the case of monochrome fonts) three bits of background color, four bits of foreground color, and a blink on/off bit. Blinking, when enabled, has a period of 100 frames (50 frames on, 50 frames off). Column 31 of each row contains row attributes. These include the fourth bit of the background color and two bits controlling double-height and double-width text. Row 15 contains global attributes, including vertical and horizontal OSD position on the screen, alpha blending, shadow/bordering, OSD rotation, color map selection, and normal/double size. Alpha blending allows the OSD display to be mixed with the incoming video signal for transparency
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OSD Block
ADE3XXX
effects. An alpha value of 255 makes the OSD opaque, while a value of 0 makes the OSD invisible, with a linear ramp of transparency between these two endpoints. Separate registers control alpha for foreground and background pixels. A fade-in/fade-out feature ramps the alpha values every six frames, starting from their current value and going up or down the sequence: 0, 16, 32, 64, 128, 192, 224, 240, 255. Row 15 also contains definitions for the four display windows. These windows define regions on the screen to which borders and shadows can be applied. (They are not analogous to windows in a GUI display, in that they do not represent four independent data displays. There is only one character map. The windows essentially define an area around which a border can be drawn or to which attributes can be assigned.) Windows also determine which of the two color tables will be used for the characters inside. Windows have a fixed precedence: window 0 has the highest precedence and window 3 the lowest. When windows overlap, the precedence determines which borders will be displayed and which color tables will be used in the overlapping area.
Figure 9: Character Attribute Map
00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 00 01 02 03 04
Row Attributes
05 06 07 08 09 10 11 12 13 14 15
Character Attributes
wa wa = window attributes ga = global attributes
ga
wa
ga
wa
00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Monochrome and color fonts are affected differently by attribute bytes. Monochrome characters are affected by shadows and borders, and have their color specified by the foreground/background attributes. Color characters interpret the attribute byte differently than monochrome characters, using it to define blinking and 90-degree rotations rather than blinking, foreground color, and background color. Color Tables There are two color tables, each containing sixteen entries by three bytes each, giving a 24-bit RGB value for each entry. Entry 0 is used for the shadow color for monochrome characters and borders. Color-table selection is made on a window-by-window basis. When writing the color table, the "row" value in the first header byte is interpreted as the color table index, while the "column" value in the second header byte encoded to select the color table (0 or 1)
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ADE3XXX
OSD Block
and the primary color (red, green, or blue). The data byte following the second header byte is written to the selected (table, index, primary) location. Font Data Font data is sent to the OSD through burst transfers. The first header byte selects the transfer type and provides three bits of the character index, while the second header byte selects transfer type "C" and gives the remaining five bits of offset. The data bytes for the character follow, given from top to bottom and left to right in the character cell. A monochrome character is 27 bytes long, with two scan-lines occupying three bytes. A color character is four times as long as a monochrome character (108 bytes), with each byte containing two four-bit pixels. Both color and monochrome fonts are 12 pixels wide and 18 high. Transfer Formats The transfer format consists of two header bytes and a variable number of data bytes. The header bytes determine the type of transfer (character, attribute, monochrome font, color font, or color table). Addressing is by row and column in the case of character or attribute transfers, and by character index in the case of font transfers. When writing to the color table, the "column" field determines the color table and R/G/B selection.
Table 23: OSD Access Header Definition
Header Byte First Bits [7:4] Description Type of data transfer. Valid values are: 0x8: screen map 0x9: color LUT 0xA: attribute map 0xC: font data all others: Reserved [3:0] For screen map or attribute map access, this is the row index. For color LUT access, this is the color index. For font data access, bits [2:0] are the MSB's of the character index. Second [7:6] Type of data burst: 0x0: A/B modes: Only one data byte follows this header byte. 0x1: C mode: All bytes following this header byte are data bytes until the serial interface indicates an end-of-transmission. The OSD internally auto-increments after each byte. In screen and attribute map access modes the column number is incremented after each byte, wrapping to the beginning of the next row once column 29 is passed and wrapping to row 0 if row 14 is passed. Either mode may be used for display and character attribute modes, except for the off-screen attributes in column 15 and row 30, which must use mode A/B. Font definition mode must use mode C. [5] [4:0] must be set to zero In screen and attribute map access modes, this is the column number. In font data access mode, this gives the 5 lsb's of the character index. In color LUT access mode, it selects the table number and color to be written: 0x0: LUT 0, red 0x1: LUT 0, green 0x2: LUT 0, blue 0x3: LUT 1, red 0x4: LUT 1, green 0x5: LUT 1, blue 0x6 - 0x7: Reserved
69/88
OSD Block
Table 24: OSD Attribute Map Definition (Sheet 1 of 2) Row
15 15 15 12 13 15
ADE3XXX
Column
[7:0] [7:0] [7] [6:5]
Bits
Description
vertical OSD position / 4 horizontal OSD position / 5 0: OSD off 1: OSD on 0x0: Plain Characters 0x1: Border Characters 0x2: Shadow Characters 0x3: Reserved Reserved 0: normal 1: flip OSD 0: Fade Off 1: Fade On 0: Normal Size 1: Double Size Foreground Alpha Blending Background Alpha Blending Window 0 Row Start Window 0 Row End Window 1 Row Start Window 1 Row End Window 2 Row Start Window 2 Row End Window 3 Row Start Window 3 Row End Window 0 Column Start Window 0 Visibility 0: Off 1: On
[4:3] [2] [1] [0] 15 15 15 19 20 0 [7:0] [7:0] [7:4] [3:0] 15 3 [7:4] [3:0] 15 6 [7:4] [3:0] 15 9 [7:4] [3:0] 15 1 [7:3] [2]
[1] [0] 15 4 [7:3] [2]
Reserved Window 0 Shadow Enable Window 1 Column Start Window 1 Visibility 0: Off 1: On
[1] [0] 15 7 [7:3] [2]
Reserved Window 1 Shadow Enable Window 2 Column Start Window 2 Visibility 0: Off 1: On
[1] [0]
Reserved Window 2 Shadow Enable
70/88
ADE3XXX
Table 24: OSD Attribute Map Definition (Sheet 2 of 2) Row
15 10
OSD Block
Column
[7:3] [2]
Bits
Description
Window 3 Column Start Window 3 Visibility 0: Off 1: On
[1] [0] 15 2 [7:3] [2:0] 15 5 [7:3] [2:0] 15 8 [7:3] [2:0] 15 11 [7:3] [2:0] 15 16 [7:6] [5:4] [3:2] [1:0] 15 17 [7:6] [5:4] [3:2] [1:0] 15 21 [7:4] [3] [2] [1] [0] 0 to 14 30 [7:3] [2] [1] [0] 0 to 14 0 to 29 [7:5]
Reserved Window 3 Shadow Enable Window 0 Column End Reserved Window 1 Column End Reserved Window 2 Column End Reserved Window 3 Column End Reserved Window 3 Shadow Width Window 2 Shadow Width Window 1 Shadow Width Window 0 Shadow Width Window 3 Shadow Height Window 2 Shadow Height Window 1 Shadow Height Window 0 Shadow Height Reserved Window 3 Color LUT Select Window 2 Color LUT Select Window 1 Color LUT Select Window 0 Color LUT Select Reserved MSB of Background Color for the Row Double High Enable for the Row Double Wide Enable for the Row 3 LSBs of Background Color for 1bpp Chars No Function for 4bpp Color Chars
[4] [3:0]
Blink Enable Foreground Color For 1bpp Chars For 4bpp Color Chars [3:2]: Reserved [1]: Flip Vertical [0]: Flip Horizontal
71/88
Flicker Block
Table 25: OSD Register Register Name
OSD_PORT
ADE3XXX
Addr
0C02
Mode
R/W
Bits
[7:0]
Default
0
Description
OSD access port
2.20
Flicker Block
The Flicker block computes correlations of the image data with potential inversion patterns of the LCD which in turn allows the microcontroller to modify the polarity signal to cancel large area flicker. This function is only useful in SmartPanel applications. The incoming image is scored against 8 vertical Walsh functions. All patterns are considered to be vertically, where horizontally the pixels are assumed to be alternating its RGB components. The scores (0 to 7) are 32-bit unsigned quantities that reflect the correlation of the programmed window area with the 8 Walsh functions. The horizontal inversion of the LCD drivers must be programmed into FLICKER_CTRL0[2:0]. The most common setting is +-+ or -+- (RGB). A calculation is completed after the number of frames programmed into the FRAME_CNT_MAX reg (0xCA03). With each frame, the calculation is performed on only a vertical strip. The width of that strip (in pixels) is determined by the value programmed in the HBLOCK_SIZE reg (0xCA02) with the following relation: strip width = 2 ^ (3 + HBLOCK_SIZE). The FREE_RUN/FREEZE_SCORES bit (FLICKER_CTRL0[4]) enables the final calculation to be captured easily by the microntroller. The internal flicker calculation continues to run -- only the update of the I2C registers is blocked when this bit is set to prevent corrupution during readout.
Table 26: Flicker Registers (Sheet 1 of 3) Register Name Addr
0x0CA1
Mode
R/W W R/W
Bits
[7:6] [5] [4]
Default
0x0 0x1 0x0 Reserved
Description
FLK_CTRL
0: straight line uniform function 1: straight line hill function (normal) 0: free run 1: freeze scores Set to a 1 when the microcontroller is reading multibyte scores to prevent update corruption. Horizontal Subpixel Polarity Inversion Pattern of LCD (even/odd pixels) 0x0: -R-G-B / +R+G+B 0x1: -R-G+B / +R+G-B 0x2: -R+G-B / +R-G+B (normal) 0x3: -R+G+B / +R-G-B 0x4: +R-G-B / -R+G+B 0x5: +R-G+B / -R+G-B (normal) 0x6: +R+G-B / -R-G+B 0x7: +R+G+B / -R-G-B
R/W
[2:0]
0x25
FLK_HBLOCK_SIZE
0x0CA2
R/W
[7:4] [3:0] 0x0
Reserved Width in pixels of the per frame scored area = 2 ^ (3+ HBLOCK_SIZE)
72/88
ADE3XXX
Table 26: Flicker Registers (Sheet 2 of 3) Register Name
FLK_FRAME_CNT_MAX
Flicker Block
Addr
0x0CA3
Mode
R/W
Bits
[7:0]
Default
0x8
Description
Number of Frames to complete one measurement total number of pixels in a line is: FRAME_CNT_MAX x (2 ^ (3 + HBLOCK_SIZE) ) example: HBLOCK_SIZE = 4; FRAME_CNT_MAX = 8; In each frame only one portion of the image is being scored. The width of that portion is 2 ^ (3 + HBLOCK_SIZE) = 128 pixels and the height is the full height of the image. Thus the total scored area after 8 frames is 128 x 8 = 1024 pixels wide.
FLK_MEAS0_0 FLK_MEAS0_1 FLK_MEAS0_2 FLK_MEAS0_3 FLK_MEAS1_0 FLK_MEAS1_1 FLK_MEAS1_2 FLK_MEAS1_3 FLK_MEAS2_0 FLK_MEAS2_1 FLK_MEAS2_2 FLK_MEAS2_3 FLK_MEAS3_0 FLK_MEAS3_1 FLK_MEAS3_2 FLK_MEAS3_3 FLK_MEAS4_0 FLK_MEAS4_1 FLK_MEAS4_2 FLK_MEAS4_3 FLK_MEAS5_0 FLK_MEAS5_1 FLK_MEAS5_2 FLK_MEAS5_3 FLK_MEAS6_1 FLK_MEAS6_2 FLK_MEAS6_3 FLK_MEAS6_4
0x0CB1 0x0CB2 0x0CB3 0x0CB4 0x0CB5 0x0CB6 0x0CB7 0x0CB8 0x0CB9 0x0CBA 0x0CBB 0x0CBC 0x0CBD 0x0CBE 0x0CBF 0x0CC0 0x0CC1 0x0CC2 0x0CC3 0x0CC4 0x0CC5 0x0CC6 0x0CC7 0x0CC8 0x0CC9 0x0CCA 0x0CCB 0x0CCC
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
[7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0]
0x0
Score for Pattern 0
0x0
Score for Pattern 1
0x0
Score for Pattern 2
0x0
Score for Pattern 3
0x0
Score for Pattern 4
0x0
Score for Pattern 5
0x0
Score for Pattern 6
73/88
Gamma Block
Table 26: Flicker Registers (Sheet 3 of 3) Register Name
FLK_MEAS7_0 FLK_MEAS7_1 FLK_MEAS7_2 FLK_MEAS7_3
ADE3XXX
Addr
0x0CCD 0x0CCE 0x0CCF 0x0CD0
Mode
R/W R/W R/W R/W
Bits
[7:0] [7:0] [7:0] [7:0]
Default
0x0
Description
Score for Pattern 7
2.21
Gamma Block
The Gamma block performs an 8 bit to 10 bit lookup table on the 3 x 8 bits (R, G, B) color data coming from SCALER.
Table 27: Gamma Registers Register Name Addr
0x0C10
Mode
R/W
Bits
[7:4] [3] [2] [1:0]
Default
0x0 0x0 0x0 0x0 Reserved
Description
GAMMA_CTRL
0: Normal 1: Disable RAM access 0: Normal 1: Test Mode Gamma Mode Select 0x0: 10b linear bypass 0x1: 8b->10b gamma table (normal) 0x2: 8b linear bypass (no interpolation) 0x3: 8b->10b gamma table (normal)
The RAMs are individually programmable (read and write) using I2C access. The memory map is as follows: I2C address 0x1000 - 0x11FF: red RAM I2C address 0x1200 - 0x13FF: green RAM I2C address 0x1400 - 0x15FF: blue RAM Even addresses are the 8-bit LSBs of the 10-bit gamma value. Odd addresses are the 2 MSBs.
2.22
APC Block
APC (formerly known as Arithmos Perfect Color) dithers an input 10-bit video stream down to 4-8 output bits. The dithering is done in space and time in such a way that the eye does not perceive objectionable artifacts such as:
q q q q
fixed dither patterns, contours, flickering pixels phase correlated flickering, which creates wave patterns known as "swimming".
74/88
ADE3XXX
Output Mux Block
Table 28: APC Registers Register Name
APC_APC0
Addr
0x0C20
Mode
Bits
[7]
Default
Reserved 0x0 0x0
Description
R/W R/W
[6:5] [4:1]
Frame Modulation Period - 1 0x0 - 0x3: 8b Out 0x4: 4-bit Output 0x5: 5-bit Output 0x6: 6-bit Output 0x7: 7-bit Output 0x8: 8-bit Output 0: normal 1: disable APC -- truncate LSBs Reserved
R/W APC_APC1 0x0C21 R/W R/W
[0] [7:2] [1] [0]
0x0
0x0 0x0
Offset the Phase LUT Offset the Dither LUT
2.23
Output Mux Block
Table 29: Output Mux Registers (Sheet 1 of 3) Register Name Addr
0x0C30
Mode
R/W
Bits
[7]
Default
0x0
Description
in 2 ppc, 0: data invert for A+B comb. 1: data invert A/B separate 0x0 - 0x4: right shift per 8b R/G/B 0x5 - 0x7: Reserved 0: normal 1: flip MSBs to LSBs 0: normal 1: swap R and B data 0: in 1 ppc, A channel active 0: in 2 ppc, Left on A, Right on B 1: in 1 ppc, B channel active 1: 2ppc, Left on B, Right on A 0: single wide, one pix/clk (ppc) 1: double wide, two pix/clk Vsync Output Polarity Hsync Output Polarity Data Enable Output Polarity Clock Output Invert Data Invert Output Polarity Data Invert Enable 0: TCON outputs set to zero 1: TCON outputs active 0: all data outputs set to zero 1: output enabled
OMUX_CTRL_0
R/W R/W R/W R/W
[6:4] [3] [2] [1]
0x0 0x0 0x0 0x0
R/W OMUX_CTRL_1 0x0C31 R/W R/W R/W R/W R/W R/W R/W R/W
[0] [7] [6] [5] [4] [3] [2] [1] [0]
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
75/88
Output Mux Block
Table 29: Output Mux Registers (Sheet 2 of 3) Register Name
OMUX_CTRL_2
ADE3XXX
Addr
0x0C32
Mode
R/W R/W R/W R/W R/W R/W R/W R/W
Bits
[7] [6] [5] [4] [3] [2] [1] [0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0]
Default
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
Description
Seperate TCON Driven Invert Enable TCON Driven Invert Pin Enable RSDS enable Per Pin Delay Enable Resync on Vsync Falling Edge Resync on Vsync Rising Edge Resync on Hsync Falling Edge Resync on Hsync Rising Edge Delay for OBA1 Delay for OBA0 Delay for OBA3 Delay for OBA2 Delay for OBA5 Delay for OBA4 Delay for OBA7 Delay for OBA6 Delay for OGA1 Delay for OGA0 Delay for OGA3 Delay for OGA2 Delay for OGA5 Delay for OGA4 Delay for OGA7 Delay for OGA6 Delay for ORA1 Delay for ORA0 Delay for ORA3 Delay for ORA2 Delay for ORA5 Delay for ORA4 Delay for ORA7 Delay for ORA6 Delay for OBB1 Delay for OBB0 Delay for OBB3 Delay for OBB2 Delay for OBB5 Delay for OBB4 Delay for OBB7 Delay for OBB6 Delay for OGB1 Delay for OGB0 Delay for OGB3 Delay for OGB2
OMUX_DLY_BA0 OMUX_ DLY_BA2 OMUX_ DLY_BA4 OMUX_ DLY_BA6 OMUX_ DLY_GA0 OMUX_ DLY_GA2 OMUX_ DLY_GA4 OMUX_ DLY_GA6 OMUX_ DLY_RA0 OMUX_ DLY_RA2 OMUX_ DLY_RA4 OMUX_ DLY_RA6 OMUX_ DLY_BB0 OMUX_ DLY_BB2 OMUX_ DLY_BB4 OMUX_ DLY_BB6 OMUX_ DLY_GB0 OMUX_ DLY_GB2
0x0C50 0x0C4F 0x0C4E 0x0C4D 0x0C4C 0x0C4B 0x0C4A 0x0C49 0x0C48 0x0C47 0x0C46 0x0C45 0x0C44 0x0C43 0x0C42 0x0C41 0x0C40 0x0C3F
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
76/88
ADE3XXX
Pulse Width Modulation (PWM) Block
Table 29: Output Mux Registers (Sheet 3 of 3)
Register Name
OMUX_ DLY_GB4 OMUX_ DLY_GB6 OMUX_ DLY_RB0 OMUX_ DLY_RB2 OMUX_ DLY_R_B4 OMUX_ DLY_R_B6 OMUX_ DLY_TCON_0 OMUX_ DLY_TCON_2 OMUX_ DLY_TCON_4 OMUX_ DLY_TCON_6 OMUX_ DLY_VS_ENAB OMUX_ DLY_CLK_HS OMUX_CTRL_3
Addr
0x0C3E 0x0C3D 0x0C3C 0x0C3B 0x0C3A 0x0C39 0x0C38 0x0C37 0x0C36 0x0C35 0x0C34 0x0C33 0x0C51
Mode
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bits
[7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:3] [2] [1] [0] [7:6]
Default
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
Description
Delay for OGB5 Delay for OGB4 Delay for OGB7 Delay for OGB6 Delay for ORB1 Delay for ORB0 Delay for ORB3 Delay for ORB2 Delay for ORB5 Delay for ORB4 Delay for ORB7 Delay for ORB6 Delay for TCON1 Delay for TCON0 Delay for TCON3 Delay for TCON2 Delay for TCON5 Delay for TCON4 Delay for TCON7 Delay for TCON6 Delay for VSYNC Delay for ENAB Delay for CLK Delay for HSYNC Reserved PWM mux mode PWM enable TCON data invert enable, with computed data invert pin. Reserved returns a value that indicates the ADE gate speed -- a function of temp and voltage higher = faster logic
OMUX_REFCOUNT
0x0C52 R
[5:0]
0x0
2.24
Pulse Width Modulation (PWM) Block
The PWM B block generates two signals to control backlight inverter switching power components directly. It is derived from XCLK and powered up independently of the DOTCLK and INCLK domains. Frequency, duty cycle, polarity and overlap/non-overlap are programmable. The output frequency can "free-run" or lock to output vsync.
77/88
Pulse Width Modulation (PWM) Block
ADE3XXX
Table 30: PWM Registers Register Name
PWM_CTRL0
Addr
0x01A0
Mode
R
Bits
[7]
Default
0x0 PWM status 0: unlocked 1: locked
Description
R/W
[6]
0x0
0: lock to CYCLES_PER_FRAME from the free run state machine 1: lock to CYCLES_PER_FRAME register setting PWM_A polarity 0: active low 1: active high
R/W
[5]
0x0
R/W
[4]
0x0
PWM_B polarity 0: active low 1: active high
R/W R/W
[3] [2]
0x0 0x0
0: normal operation 1: force PWM outputs to polarity settings 0: change period or duty cycle at the end of the current cycle 1: smooth change, period or duty cycle increment/decrement every PWM_STEP_DELAY cycle 0: free run 1: lock to out_vsync 0: disable PWM output 1: enable PWM output Lock 2nd order gain (power of 2) 0x0 = max 0x3 = typical 0xF = min
R/W R/W PWM_CTRL1 0x01A1 R/W
[1] [0] [7:4]
0x0 0x0 0x0
R/W
[3:0]
0x0
Lock gain (power of 2) 0x0 = max 0x6 = typical 0xF = min Period-2 in Free-running mode, in XCLKs
PWM_PERIOD_L PWM_PERIOD_H PWM_DUTY_L PWM_DUTY_H PWM_OVERLAP_L PWM_OVERLAP_H PWM_STEP_DELAY
0x01A2 0x01A3 0x01A4 0x01A5 0x01A6 0x01A7 0x01A8
R/W R/W R/W R/W R/W R/W R/W
[7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0]
0x0
0x0
Duty cycle of PWM in XCLKs
0x0
Non-overlap of PWMs in XCLKs
0x0
In smooth change mode, the number of cycles skipped before the period/duty registers are incremented/decremented The number of cycles per frame in frame lock mode when not using the internally generated cycles per frame from a previous freerun mode
PWM_CYCLES_PER_FRAME_L PWM_CYCLES_PER_FRAME_H
0x01A9 0x01AA
R/W R/W
[7:0] [7:0]
0x0
78/88
ADE3XXX
DFT Block
2.25
DFT Block
Table 31: DFT Registers (Sheet 1 of 2) Register Name Addr
0x0F00 R/W R/W R/W R/W
Mode
Bits
[7:4] [3] [2] [1] [0] [7:6] [5:0] [7:6] [5:0] [7:6] [5:0] [7:6] [5:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:3] [2] [1] [0] [7:5] [4] [3] [2:0] [7:6] [0] [7] [6] [5] [4] [3] [2] [1] [0]
Default
Reserved 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
Description
trigger video bus MFSR enable output pin MFSR clear output pin MFSR output pin test override Reserved mux selector for output porta/b and syncs Reserved mux selector for synchronous digital debug bus divide-by selector for clocks to OCLK pin fout = selected clock / (2 ^ value) mux selector for clocks to OCLK pin divide-by selector for clocks to CLKOUT pin fout = selected clock / (2 ^ value) mux selector for clocks to CLKOUTpin disable porta red output in test mode disable porta green output in test mode disable porta blue output in test mode disable portb red output in test mode disable portb green output in test mode disable portb blue output in test mode disable tcon bits [4:0] in test mode disable vert sync output in test mode disable data enab output in test mode disable horz sync output in test mode Reserved disable CLKOUT output in test mode disable OCLK output in test mode disable tcon bits [7:5] in test mode Reserved internal stimulus bus enable SCL test stimulus enable HDCP test stimulus enable DVI test mode enable DVI blue test stimulus enable DVI green test stimulus enable
DFT_TEST_MODE
DFT_MUX_OUT_MODE DFT_FLOP_OUT_MODE
0x0F01 R/W 0x0F02 R/W
DFT_CLK_0UT_MODE
0x0F03
R/W R/W
DFT_CLK_1_MODE DFT_CLK_2_MODE DFT_OUT_DISAB_0 DFT_OUT_DISAB_1 DFT_OUT_DISAB_2 DFT_OUT_DISAB_3 DFT_OUT_DISAB_4 DFT_OUT_DISAB_5 DFT_OUT_DISAB_6
0x0F04 0x0F05 0x0F06 0x0F07 0x0F08 0x0F09 0x0F0A 0x0F0B 0x0F0C
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
DFT_OUT_DISAB_7
0x0F0D R/W R/W R/W
DFT_STIM_CTRL DFT_STIM_EN_0
0x0F0E R/W 0x0F0F R/W R/W R/W R/W R/W R/W R/W R/W
0x0 0x0 0x0
DVI red test stimulus enable ADC test stimulus enable YUV test stimulus enable
79/88
IC RAM Addresses
Table 31: DFT Registers (Sheet 2 of 2) Register Name
DFT_STIM_EN_1
ADE3XXX
Addr
0x0F10
Mode
R/W R/W R/W R/W R/W R/W
Bits
[7:6] [5] [4] [3] [2] [1] [0] [7:6] [5] [4] [3] [2] [1] [0] [7:6] [5] [4] [3] [2] [1] [0] [7] [6] [5] [4] [3] [2] [1] [0] [7:1] [0]
Default
Reserved 0x0 0x0 0x0 0x0 0x0 0x0
Description
TCON test bypass OMUX test stimulus enable APC test stimulus enable OSD test stimulus enable SCL bypass PGEN test stimulus enable Reserved gamma RAM BIST end OSD CS RAM BIST end OSD DRB RAM BIST OSD MB RAM BIST end SCL coeff. RAM BIST end SCL line buffer RAM BIST end Reserved SCL coeff RAM 2 BIST fail SCL coeff RAM 1 BIST fail SCL line buffer 4 BIST fail SCL line buffer 3 BIST fail SCL line buffer 2 BIST fail SCL line buffer 1 BIST fail Reserved Gamma blue RAM BIST fail Gamma green RAM BIST fail Gamma red RAM BIST fail OSD CS RAM1 BIST fail OSD CS RAM 2 BIST fail OSD DRB RAM BIST fail OSD MB RAM BIST fail Reserved done signal
DFT_BIST_STATUS
0x0F11 R R R R R R
DFT_BIST_RESULT_0
0x0F12 R R R R R R
DFT_BIST_RESULT_1
0x0F13 R R R R R R R
DFT_MFSR_DONE DFT_MFSR_SIG_0 DFT_MFSR_SIG_1 DFT_MFSR_SIG_2 DFT_MFSR_SIG_3
0x0F14 R 0x0F15 0x0F16 0x0F17 0x0F18 R R R R
[7:0] [7:0] [7:0] [7:0]
0x0
Video Bus MFSR
2.26
IC RAM Addresses
Table 32: IC RAM Addresses Name Start Addr.
0x1000 0x1200 0x1400
End Addr.
0x11FF 0x13FF 0x15FF
Description
Gamma LUT, Red, LSB0,MSB0,LSB1,... (256x10) Gamma LUT, Green, (256x10) Gamma LUT, Blue, (256x10)
GAM_RED GAM_GREEN GAM_BLUE
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ADE3XXX
Table 32: IC RAM Addresses Name
OSD_MB OSD_CS OSD_DRB SCL_COEFF SCL_LINE1 SCL_LINE2 SCL_LINE3 SCL_LINE4
IC RAM Addresses
Start Addr.
0x1700 0x3000 0x6000 0x9000 0x9900 0xA800 0xB700 0xC600
End Addr.
0x175F 0x5F3F 0x647F 0x98FF 0xA7FF 0xB6FF 0xC5FF 0xD4FF
Description
OSD Color LUTs (32x24) OSD Character Map (1344x36x2 copies) OSD Screen Map (1152x8) Scaler Coefficient RAM (256x36x2 copies) Scaler Line Buffer 1 (1280x24) Scaler Line Buffer 2 (1280x24) Scaler Line Buffer 3 (1280x24) Scaler Line Buffer 4 (1280x24)
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Absolute Maximum Ratings
ADE3XXX
3
3.1
Electrical Specifications
Absolute Maximum Ratings
Symbol
AVDD18 DVDD18 XVDD18 LVDD18 AVDD33 DVDD33 VIN TSTG Supply Voltage
Parameter
Min
Typ
Max
1.95
Unit
V
Supply Voltage Max voltage on 5 volt tolerant input pins Storage Temperature -40
3.6 6.1 +150
V V C
3.2
Power Consumption Matrices
Table 33: ADE3100
Symbol
Parameter
Supply Current (Analog Input, XGA@75Hz, 78.75MHz)
Min
Typ*
Max**
Unit
IAVDD18 IDVDD18 IAVDD33 IDVDD33
1.8V analog supply (IAVDD18) 1.8V digital supply (IDVDD18) 3.3V analog supply (IAVDD33) 3.3V digital supply (IDVDD33) Supply Current (DVI Input, XGA@75Hz, 78.75MHz)
188 213 109 64
197 240 113 69
mA mA mA mA
IAVDD18 IDVDD18 IAVDD33 IDVDD33
1.8V analog supply (IAVDD18) 1.8V digital supply (IDVDD18) 3.3V analog supply (IAVDD33) 3.3V digital supply (IDVDD33) Supply Current (Stand By Mode)
57 222 109 59
67 250 115 67
mA mA mA mA
IAVDD18 IDVDD18 IAVDD33 IDVDD33 PTOTANA PTOTDVI PSTANDBY
1.8V analog supply (IAVDD18) 1.8V digital supply (IDVDD18) 3.3V analog supply (IAVDD33) 3.3V digital supply (IDVDD33) Total Power Consumption (Analog Input, XGA@75Hz, 78.75MHz) Total Power Consumption (DVI Input, XGA@75Hz, 78.75MHz) Total Power Consumption (Stand By Mode)
3.4 3.9 0.5 2.5 1.55 1.4 23.2
3.9 5.4 3.9 3.0 1.85 1.73 39.4
mA mA mA mA W W mW
* **
Measured at nominal voltage supplies Measured at +10% voltage supplies
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ADE3XXX
Nominal Operating Conditions
Table 34: ADE3300 Symbol Parameter
Supply Current (Analog Input, XGA@75Hz, 135MHz) IAVDD18 IDVDD18 IAVDD33 IDVDD33 1.8V analog supply (IAVDD18) 1.8V digital supply (IDVDD18) 3.3V analog supply (IAVDD33) 3.3V digital supply (IDVDD33) Supply Current (DVI Input, XGA@75Hz, 135MHz) IAVDD18 IDVDD18 IAVDD33 IDVDD33 1.8V analog supply (IAVDD18) 1.8V digital supply (IDVDD18) 3.3V analog supply (IAVDD33) 3.3V digital supply (IDVDD33) Supply Current (Stand By Mode) IAVDD18 IDVDD18 IAVDD33 IDVDD33 PTOTANA PTOTDVI PSTANDBY 1.8V analog supply (IAVDD18) 1.8V digital supply (IDVDD18) 3.3V analog supply (IAVDD33) 3.3V digital supply (IDVDD33) Total Power Consumption (Analog Input, XGA@75Hz, 135MHz) Total Power Consumption (DVI Input, XGA@75Hz, 135MHz) Total Power Consumption (Stand By Mode) 3.4 3.9 3.9 3.9 1.55 1.4 38.9 1.85 1.73 mA mA mA mA W W mW 58 371 114 77 68 415 120 94 mA mA mA mA 193 346 109 67 199 380 113 82 mA mA mA mA
Min
Typ*
Max**
Unit
* **
Measured at nominal voltage supplies Measured at +10% voltage supplies
3.3
Nominal Operating Conditions
Symbol
AVDD18 DVDD18 XVDD18 LVDD18 AVDD33 DVDD33 fXTAL TOPER Supply Voltage
Parameter
Min
1.71
Typ
1.8
Max
1.89
Unit
V
Supply Voltage Crystal Frequency Ambient Operating Temperature
3.135
3.3 27
3.465
V MHz
0
+70
C
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Preliminary Thermal Data
ADE3XXX
3.4
Preliminary Thermal Data
Symbol
RthJA
Parameter
Junction-to-Ambient Thermal Resistance
Min
Typ
Max
25
Unit
C/W
3.5
Preliminary DC Specifications
Test Conditions: DVDD33 = AVDD33 = 3.3V, DVDD18 = AVDD18 = XVDD18 = LVDD18 = 1.8V, and TAMB = 25C
3.5.1
LVTTL 5 Volt Tolerant Inputs With Hysteresis
YUV[0:7], YUVCLK, HSYNC, VSYNC, CSYNC, TCON_IN, SCL, RESETN
Symbol
VIH VIL VHYST
Parameter
High Level Input voltage Low Level Input voltage Schmitt trigger hysteresis
Condition
Min
2.0
Typ
Max
Unit
V
0.8 0.4
V V
3.5.2
LVTTL 5 Volt Tolerant Inputs
XCLK_EN
Symbol
VIH VIL
Parameter
High Level Input voltage Low Level Input voltage
Condition
Min
2.0
Typ
Max
Unit
V
0.8
V
3.5.3
LVTTL 5 Volt Tolerant I/O With Hysteresis
SDA
Symbol
VIH VIL VHYST
Parameter
High Level Input voltage Low Level Input voltage Schmitt trigger hysteresis
Condition
Min
2.0
Typ
Max
Unit
V
0.8 0.4
V V
3.5.4
LVTTL Outputs
OBA[0:7], OGA[0:7], ORA[0:7], OBB[0:7], OGB[0:7], ORB[0:7], OHS, OVS, ODE, OCLK
Symbol
VIH VIL IIH
Parameter
High Level Input voltage Low Level Input voltage High Level Input current
Condition
Min
2.0
Typ
Max
Unit
V
0.8 VIN = VDD -10
V A
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ADE3XXX
Symbol
IIL
Preliminary AC Specifications
Parameter
Low Level Input current
Condition
VIN = 0V
Min
Typ
Max
10
Unit
A
3.6
Preliminary AC Specifications
Symbol Parameter
DVI input pixel frequency DVI differential input voltage DVI input common mode voltage DVI input voltage When Tx disabled or disconnected RX powered down 45 100 1.1 50 200 1.3
Condition
Min
20 150 AVDD33 - 0.3 AVDD33 - 0.01
Typ
Max
140 1200 AVDD33 - 0.037 AVDD33 + 0.01
Unit
MHz mV V V
fDVI Vdvi_diff Vdvi_icm Vdvi_vin
Idvi_leak Rdvi_term Vrsds_diff Vrsrs_cm
DVI input leackage current
10 55 400 1.5
A Ohm mV V
DVI input termination resistance Rext = 470 Ohms RSDS differential output voltage RSDS mode RSDS common mode output voltage 680 ohm + 50 ohm external termination to 1.3V CL = 30pF
Trise, Tfall INL DNL Vadc_in ENOB
RSDS transition time to 90% ADC integral nonlinearity (9b) ADC differential nonlinearity (9b) ADC input voltage range ADC effective number of bits
3 1.5
ns LSB LSB
no missing codes 0.5 135MSPS Input = 65MHz sine at 95% FS
1.5 1 7.5
Vp-p bits
Radc_in Cadc_in Fadc
ADC input resistance ADC input capacitance ADC sample frequency 20
200 8 140
Kohms pF MHz
ADC gain step ADC offset step Cadc_ext
ADC gain step size ADC offset step size ADC external AC coupling cap
0.05 4 0.1
dB mV uF
85/88
Preliminary AC Specifications
ADE3XXX
4
Package Mechanical Data
D D1 A D3 A1 156 157 105 104 0.076 mm .003 inch Seating Plane B B A2
E3
E1
Pin 1 Identification
208 1 Exact shape of each corner is optional e 52
53 C
L1 L
E
0.25 mm .010 in. Gage Plane K
Dimensions (mm) Min.
A A1 A2 B C D D1 D3 e E E1 E3 L L1 K 0.25 3.20 0.17 0.09
Dimensions (inches) Max.
4.10 0.40 3.60 0.27 0.20
Typ.
0.30 3.40
Min.
0.010 0.126 0.007 0.003
Typ.
Max.
0.161
0.134
0.142 0.011 0.008
0.45
30.60 28.00 25.50 0.50 30.60 28.00 25.50 0.60 1.30
0.75
0.018
1.205 1.102 1.004 0.020 1.205 1.102 1.004 0.024 0.051
0.029
0 (min.), 3.5(typ.), 7(max.)
Note:
Exact shape of each corner is optional
86/88
ADE3XXX
Preliminary AC Specifications
5
Revision History
Table 35: Summary of Modifications
Version
0.1 1.0 1.1 1.2 1.3 1.4
Date
22 Oct. 2002 25 Nov 2002 05 Feb 2003 18 Apr 2003 10 July 2003 17 July 2003 First Issue
Description of Modification
Update of registers SMEAS_V_CTRL, SMUX_CTRL0 and FLK_CTRL. Changed "Projection Display Engine" to "LCD Display Engine" on page 1. Changed header name "ADE3500X/3600X" to "ADE3XXX" on page 2. Deletion of YUV port information. Inclusion of Section 3.2: Power Consumption Matrices on page 82. Re-insertion of YUV port information.
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ADE3XXX
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 2003 STMicroelectronics - All Rights Reserved Purchase of I2C Components by STMicroelectronics conveys a license under the Philips I2C Patent. Rights to use these components in an I2C system is granted provided that the system conforms to the I2C Standard Specification as defined by Philips. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States.
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